x86/perf/core: Add pebs_capable to store valid PEBS_COUNTER_MASK value

The value of pebs_counter_mask will be accessed frequently
for repeated use in the intel_guest_get_msrs(). So it can be
optimized instead of endlessly mucking about with branches.

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Message-Id: <20220411101946.20262-7-likexu@tencent.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index b56ead52790a61eee1cff8888ac0a9f65d1c52cf..8c9cb41fc20a5d01d74db313b6a3d627720654ef 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2932,10 +2932,7 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status)
         * counters from the GLOBAL_STATUS mask and we always process PEBS
         * events via drain_pebs().
         */
-       if (x86_pmu.flags & PMU_FL_PEBS_ALL)
-               status &= ~cpuc->pebs_enabled;
-       else
-               status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
+       status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
 
        /*
         * PEBS overflow sets bit 62 in the global status register
@@ -3981,10 +3978,7 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
        arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
        arr[0].host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
        arr[0].guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask;
-       if (x86_pmu.flags & PMU_FL_PEBS_ALL)
-               arr[0].guest &= ~cpuc->pebs_enabled;
-       else
-               arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
+       arr[0].guest &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
        *nr = 1;
 
        if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) {
@@ -5692,6 +5686,7 @@ __init int intel_pmu_init(void)
        x86_pmu.events_mask_len         = eax.split.mask_length;
 
        x86_pmu.max_pebs_events         = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
+       x86_pmu.pebs_capable            = PEBS_COUNTER_MASK;
 
        /*
         * Quirk: v2 perfmon does not report fixed-purpose events, so
@@ -5876,6 +5871,7 @@ __init int intel_pmu_init(void)
                x86_pmu.pebs_aliases = NULL;
                x86_pmu.pebs_prec_dist = true;
                x86_pmu.lbr_pt_coexist = true;
+               x86_pmu.pebs_capable = ~0ULL;
                x86_pmu.flags |= PMU_FL_HAS_RSP_1;
                x86_pmu.flags |= PMU_FL_PEBS_ALL;
                x86_pmu.get_event_constraints = glp_get_event_constraints;
@@ -6233,6 +6229,7 @@ __init int intel_pmu_init(void)
                x86_pmu.pebs_aliases = NULL;
                x86_pmu.pebs_prec_dist = true;
                x86_pmu.pebs_block = true;
+               x86_pmu.pebs_capable = ~0ULL;
                x86_pmu.flags |= PMU_FL_HAS_RSP_1;
                x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
                x86_pmu.flags |= PMU_FL_PEBS_ALL;
@@ -6278,6 +6275,7 @@ __init int intel_pmu_init(void)
                x86_pmu.pebs_aliases = NULL;
                x86_pmu.pebs_prec_dist = true;
                x86_pmu.pebs_block = true;
+               x86_pmu.pebs_capable = ~0ULL;
                x86_pmu.flags |= PMU_FL_HAS_RSP_1;
                x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
                x86_pmu.flags |= PMU_FL_PEBS_ALL;

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 07fdef4f9ad259a6200dd6e7855b2018b8eb8ce4..09c68265b577d7c2e4f85fcbe3e46ffc8dc5e757 100644 (file)
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -828,6 +828,7 @@ struct x86_pmu {
        void            (*pebs_aliases)(struct perf_event *event);
        unsigned long   large_pebs_flags;
        u64             rtm_abort_event;
+       u64             pebs_capable;
 
        /*
         * Intel LBR