/*
- * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
int stm32mp_map_ddr_non_cacheable(void);
int stm32mp_unmap_ddr(void);
-/* Functions to save and get boot peripheral info */
-void stm32_save_boot_interface(uint32_t interface, uint32_t instance);
+/* Function to save boot info */
+void stm32_save_boot_info(boot_api_context_t *boot_context);
+/* Function to get boot peripheral info */
void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance);
-
-/* Functions to save and get boot authentication status and partition used */
-void stm32_save_boot_auth(uint32_t auth_status, uint32_t boot_partition);
+/* Function to get BOOT_MODE backup register address */
+uintptr_t stm32_get_bkpr_boot_mode_addr(void);
#if PSA_FWU_SUPPORT
void stm32mp1_fwu_set_boot_idx(void);
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <drivers/st/stm32_console.h>
#include <drivers/st/stm32mp_clkfunc.h>
#include <drivers/st/stm32mp_reset.h>
+#include <lib/mmio.h>
#include <lib/smccc.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#define HEADER_VERSION_MAJOR_MASK GENMASK(23, 16)
#define RESET_TIMEOUT_US_1MS 1000U
+#define BOOT_AUTH_MASK GENMASK_32(23, 20)
+#define BOOT_AUTH_SHIFT 20
+#define BOOT_PART_MASK GENMASK_32(19, 16)
+#define BOOT_PART_SHIFT 16
+#define BOOT_ITF_MASK GENMASK_32(15, 12)
+#define BOOT_ITF_SHIFT 12
+#define BOOT_INST_MASK GENMASK_32(11, 8)
+#define BOOT_INST_SHIFT 8
+
static console_t console;
uintptr_t plat_get_ns_image_entrypoint(void)
{
return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK);
}
+
+void stm32_save_boot_info(boot_api_context_t *boot_context)
+{
+ uint32_t auth_status;
+
+ assert(boot_context->boot_interface_instance <= (BOOT_INST_MASK >> BOOT_INST_SHIFT));
+ assert(boot_context->boot_interface_selected <= (BOOT_ITF_MASK >> BOOT_ITF_SHIFT));
+ assert(boot_context->boot_partition_used_toboot <= (BOOT_PART_MASK >> BOOT_PART_SHIFT));
+
+ switch (boot_context->auth_status) {
+ case BOOT_API_CTX_AUTH_NO:
+ auth_status = 0x0U;
+ break;
+
+ case BOOT_API_CTX_AUTH_SUCCESS:
+ auth_status = 0x2U;
+ break;
+
+ case BOOT_API_CTX_AUTH_FAILED:
+ default:
+ auth_status = 0x1U;
+ break;
+ }
+
+ clk_enable(TAMP_BKP_REG_CLK);
+
+ mmio_clrsetbits_32(stm32_get_bkpr_boot_mode_addr(),
+ BOOT_ITF_MASK | BOOT_INST_MASK | BOOT_PART_MASK | BOOT_AUTH_MASK,
+ (boot_context->boot_interface_instance << BOOT_INST_SHIFT) |
+ (boot_context->boot_interface_selected << BOOT_ITF_SHIFT) |
+ (boot_context->boot_partition_used_toboot << BOOT_PART_SHIFT) |
+ (auth_status << BOOT_AUTH_SHIFT));
+
+ clk_disable(TAMP_BKP_REG_CLK);
+}
+
+void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance)
+{
+ static uint32_t itf;
+
+ if (itf == 0U) {
+ clk_enable(TAMP_BKP_REG_CLK);
+
+ itf = mmio_read_32(stm32_get_bkpr_boot_mode_addr()) &
+ (BOOT_ITF_MASK | BOOT_INST_MASK);
+
+ clk_disable(TAMP_BKP_REG_CLK);
+ }
+
+ *interface = (itf & BOOT_ITF_MASK) >> BOOT_ITF_SHIFT;
+ *instance = (itf & BOOT_INST_MASK) >> BOOT_INST_SHIFT;
+}
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
panic();
}
- stm32_save_boot_interface(boot_context->boot_interface_selected,
- boot_context->boot_interface_instance);
- stm32_save_boot_auth(boot_context->auth_status,
- boot_context->boot_partition_used_toboot);
+ stm32_save_boot_info(boot_context);
#if STM32MP_USB_PROGRAMMER && STM32MP15
/* Deconfigure all UART RX pins configured by ROM code */
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
******************************************************************************/
#define TAMP_BASE U(0x5C00A000)
#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
+#define TAMP_BKP_REG_CLK RTCAPB
#define TAMP_COUNTR U(0x40)
#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#if STM32MP15
#define TAMP_BOOT_MODE_BACKUP_REG_ID U(20)
#endif
-#define TAMP_BOOT_MODE_ITF_MASK GENMASK(15, 8)
-#define TAMP_BOOT_MODE_ITF_SHIFT 8
-#define TAMP_BOOT_MODE_AUTH_MASK GENMASK(23, 16)
-#define TAMP_BOOT_MODE_AUTH_SHIFT 16
/*
* Backup register to store fwu update information.
}
#endif
-void stm32_save_boot_interface(uint32_t interface, uint32_t instance)
+uintptr_t stm32_get_bkpr_boot_mode_addr(void)
{
- uintptr_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
-
- clk_enable(RTCAPB);
-
- mmio_clrsetbits_32(bkpr_itf_idx,
- TAMP_BOOT_MODE_ITF_MASK,
- ((interface << 4) | (instance & 0xFU)) <<
- TAMP_BOOT_MODE_ITF_SHIFT);
-
- clk_disable(RTCAPB);
-}
-
-void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance)
-{
- static uint32_t itf;
-
- if (itf == 0U) {
- uintptr_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
-
- clk_enable(RTCAPB);
-
- itf = (mmio_read_32(bkpr) & TAMP_BOOT_MODE_ITF_MASK) >>
- TAMP_BOOT_MODE_ITF_SHIFT;
-
- clk_disable(RTCAPB);
- }
-
- *interface = itf >> 4;
- *instance = itf & 0xFU;
-}
-
-void stm32_save_boot_auth(uint32_t auth_status, uint32_t boot_partition)
-{
- uint32_t boot_status = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
-
- clk_enable(RTCAPB);
-
- mmio_clrsetbits_32(boot_status,
- TAMP_BOOT_MODE_AUTH_MASK,
- ((auth_status << 4) | (boot_partition & 0xFU)) <<
- TAMP_BOOT_MODE_AUTH_SHIFT);
-
- clk_disable(RTCAPB);
+ return tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
}
#if PSA_FWU_SUPPORT