clk: qcom: ipq8074: set BRANCH_HALT_DELAY flag for UBI clocks

Currently, attempting to enable the UBI clocks will cause the stuck at
off warning to be printed and clk_enable will fail.

[   14.936694] gcc_ubi1_ahb_clk status stuck at 'off'

Downstream 5.4 QCA kernel has fixed this by seting the BRANCH_HALT_DELAY
flag on UBI clocks, so lets do the same.

Fixes: 054e59f95fbe ("clk: qcom: ipq8074: add NSS clocks")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-6-robimarko@gmail.com

diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index c964e43ba68adf92b4bc5cdfdf97dd7455782659..85076c1383c7ae2fee6718b3b1e9eae65aaac703 100644 (file)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -3372,6 +3372,7 @@ static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {
 
 static struct clk_branch gcc_ubi0_ahb_clk = {
        .halt_reg = 0x6820c,
+       .halt_check = BRANCH_HALT_DELAY,
        .clkr = {
                .enable_reg = 0x6820c,
                .enable_mask = BIT(0),
@@ -3389,6 +3390,7 @@ static struct clk_branch gcc_ubi0_ahb_clk = {
 
 static struct clk_branch gcc_ubi0_axi_clk = {
        .halt_reg = 0x68200,
+       .halt_check = BRANCH_HALT_DELAY,
        .clkr = {
                .enable_reg = 0x68200,
                .enable_mask = BIT(0),
@@ -3406,6 +3408,7 @@ static struct clk_branch gcc_ubi0_axi_clk = {
 
 static struct clk_branch gcc_ubi0_nc_axi_clk = {
        .halt_reg = 0x68204,
+       .halt_check = BRANCH_HALT_DELAY,
        .clkr = {
                .enable_reg = 0x68204,
                .enable_mask = BIT(0),
@@ -3423,6 +3426,7 @@ static struct clk_branch gcc_ubi0_nc_axi_clk = {
 
 static struct clk_branch gcc_ubi0_core_clk = {
        .halt_reg = 0x68210,
+       .halt_check = BRANCH_HALT_DELAY,
        .clkr = {
                .enable_reg = 0x68210,
                .enable_mask = BIT(0),
@@ -3440,6 +3444,7 @@ static struct clk_branch gcc_ubi0_core_clk = {
 
 static struct clk_branch gcc_ubi0_mpt_clk = {
        .halt_reg = 0x68208,
+       .halt_check = BRANCH_HALT_DELAY,
        .clkr = {
                .enable_reg = 0x68208,
                .enable_mask = BIT(0),
@@ -3457,6 +3462,7 @@ static struct clk_branch gcc_ubi0_mpt_clk = {
 
 static struct clk_branch gcc_ubi1_ahb_clk = {
        .halt_reg = 0x6822c,
+       .halt_check = BRANCH_HALT_DELAY,
        .clkr = {
                .enable_reg = 0x6822c,
                .enable_mask = BIT(0),
@@ -3474,6 +3480,7 @@ static struct clk_branch gcc_ubi1_ahb_clk = {
 
 static struct clk_branch gcc_ubi1_axi_clk = {
        .halt_reg = 0x68220,
+       .halt_check = BRANCH_HALT_DELAY,
        .clkr = {
                .enable_reg = 0x68220,
                .enable_mask = BIT(0),
@@ -3491,6 +3498,7 @@ static struct clk_branch gcc_ubi1_axi_clk = {
 
 static struct clk_branch gcc_ubi1_nc_axi_clk = {
        .halt_reg = 0x68224,
+       .halt_check = BRANCH_HALT_DELAY,
        .clkr = {
                .enable_reg = 0x68224,
                .enable_mask = BIT(0),
@@ -3508,6 +3516,7 @@ static struct clk_branch gcc_ubi1_nc_axi_clk = {
 
 static struct clk_branch gcc_ubi1_core_clk = {
        .halt_reg = 0x68230,
+       .halt_check = BRANCH_HALT_DELAY,
        .clkr = {
                .enable_reg = 0x68230,
                .enable_mask = BIT(0),
@@ -3525,6 +3534,7 @@ static struct clk_branch gcc_ubi1_core_clk = {
 
 static struct clk_branch gcc_ubi1_mpt_clk = {
        .halt_reg = 0x68228,
+       .halt_check = BRANCH_HALT_DELAY,
        .clkr = {
                .enable_reg = 0x68228,
                .enable_mask = BIT(0),