drm/i915/gtt: allow overriding the pt alignment

On some platforms we have alignment restrictions when accessing LMEM
from the GTT. In the next few patches we need to be able to modify the
page-tables directly via the GTT itself.

Suggested-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220218184752.7524-10-ramalingam.c@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 5e038cef0d9fc111e47a69f3cc35fe196308233d..9d83c2d3959c44b3feab10ddc962ea3521cf3047 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -200,6 +200,14 @@ void *__px_vaddr(struct drm_i915_gem_object *p);
 struct i915_vm_pt_stash {
        /* preallocated chains of page tables/directories */
        struct i915_page_table *pt[2];
+       /*
+        * Optionally override the alignment/size of the physical page that
+        * contains each PT. If not set defaults back to the usual
+        * I915_GTT_PAGE_SIZE_4K. This does not influence the other paging
+        * structures. MUST be a power-of-two. ONLY applicable on discrete
+        * platforms.
+        */
+       int pt_sz;
 };
 
 struct i915_vma_ops {
@@ -595,7 +603,7 @@ void free_scratch(struct i915_address_space *vm);
 
 struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz);
 struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz);
-struct i915_page_table *alloc_pt(struct i915_address_space *vm);
+struct i915_page_table *alloc_pt(struct i915_address_space *vm, int sz);
 struct i915_page_directory *alloc_pd(struct i915_address_space *vm);
 struct i915_page_directory *__alloc_pd(int npde);
 

diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 043652dc689271a83244148f1534e3ffd39ab5fc..d91e2beb751772d6b3ffd9aff9cd397ecf97d263 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -12,7 +12,7 @@
 #include "gen6_ppgtt.h"
 #include "gen8_ppgtt.h"
 
-struct i915_page_table *alloc_pt(struct i915_address_space *vm)
+struct i915_page_table *alloc_pt(struct i915_address_space *vm, int sz)
 {
        struct i915_page_table *pt;
 
@@ -20,7 +20,7 @@ struct i915_page_table *alloc_pt(struct i915_address_space *vm)
        if (unlikely(!pt))
                return ERR_PTR(-ENOMEM);
 
-       pt->base = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K);
+       pt->base = vm->alloc_pt_dma(vm, sz);
        if (IS_ERR(pt->base)) {
                kfree(pt);
                return ERR_PTR(-ENOMEM);
@@ -221,17 +221,25 @@ int i915_vm_alloc_pt_stash(struct i915_address_space *vm,
                           u64 size)
 {
        unsigned long count;
-       int shift, n;
+       int shift, n, pt_sz;
 
        shift = vm->pd_shift;
        if (!shift)
                return 0;
 
+       pt_sz = stash->pt_sz;
+       if (!pt_sz)
+               pt_sz = I915_GTT_PAGE_SIZE_4K;
+       else
+               GEM_BUG_ON(!IS_DGFX(vm->i915));
+
+       GEM_BUG_ON(!is_power_of_2(pt_sz));
+
        count = pd_count(size, shift);
        while (count--) {
                struct i915_page_table *pt;
 
-               pt = alloc_pt(vm);
+               pt = alloc_pt(vm, pt_sz);
                if (IS_ERR(pt)) {
                        i915_vm_free_pt_stash(vm, stash);
                        return PTR_ERR(pt);