drm/vc4: hdmi: Reset HDMI MISC_CONTROL register

The HDMI block can repeat pixels for double clocked modes,
and the firmware is now configuring the block to do this as
the PV is doing it incorrectly when at 2pixels/clock.
If the kernel doesn't reset it then we end up with strange
modes.

Reset MISC_CONTROL.

Fixes: e40b36e7391d ("drm/vc4: hdmi: Support the BCM2711 HDMI controllers")
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20220613144800.326124-22-maxime@cerno.tech
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 9f49dd9b9d1b588355ab6f336f9e790b8d7f22f1..cc700ed51075fc069673b56319e54a48095c1743 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -79,6 +79,9 @@
 #define VC5_HDMI_VERTB_VSPO_SHIFT              16
 #define VC5_HDMI_VERTB_VSPO_MASK               VC4_MASK(29, 16)
 
+#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT  0
+#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK   VC4_MASK(3, 0)
+
 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE          BIT(0)
 
 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT     8
@@ -1117,6 +1120,11 @@ static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
        reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
        HDMI_WRITE(HDMI_GCP_CONFIG, reg);
 
+       reg = HDMI_READ(HDMI_MISC_CONTROL);
+       reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
+       reg |= VC4_SET_FIELD(0, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
+       HDMI_WRITE(HDMI_MISC_CONTROL, reg);
+
        HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 
        spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
index a040356b6bdc1a99e22f6edc7cc10e190e9d26ba..549cc63dab39bc6fc1c3140fbcb850967eeffc9d 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
@@ -127,6 +127,7 @@ enum vc4_hdmi_field {
        HDMI_VERTB0,
        HDMI_VERTB1,
        HDMI_VID_CTL,
+       HDMI_MISC_CONTROL,
 };
 
 struct vc4_hdmi_register {
@@ -237,6 +238,7 @@ static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi0_fields[] = {
        VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
        VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
        VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
+       VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100),
        VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
        VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
        VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
@@ -319,6 +321,7 @@ static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi1_fields[] = {
        VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
        VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
        VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
+       VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100),
        VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
        VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
        VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),