Note that, its up to the individual architectures to implement
this functionality.
+config SYS_IMMR
+ hex
+ depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
+ default 0xFF000000 if MPC8xx
+ default 0xF0000000 if ARCH_MPC8313
+ default 0xE0000000 if MPC83xx && !ARCH_MPC8313
+ default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
+ default SYS_CCSRBAR_DEFAULT
+ help
+ Address for the Internal Memory-Mapped Registers (IMMR) window used
+ to configure the features of many Freescale / NXP SoCs.
+
config SKIP_LOWLEVEL_INIT
bool "Skip the calls to certain low level initialization functions"
depends on ARM || NDS32 || MIPS || RISCV
#include <linux/bitops.h>
#endif
-#define CONFIG_SYS_IMMR 0x01000000
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
#define __ARCH_FSL_LSCH3_IMMAP_H_
-#define CONFIG_SYS_IMMR 0x01000000
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
#define OCRAM_BASE_S_ADDR 0x10010000
#define OCRAM_S_SIZE 0x00010000
-#define CONFIG_SYS_IMMR 0x01000000
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
select SYS_CACHE_SHIFT_5
select FSL_ELBC
-config SYS_IMMR
- hex "Value for IMMR"
- default 0xE0000000
- help
- Address for the Internal Memory-Mapped Registers (IMMR) window used
- to configure the features of the SoC.
-
source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig"
source "arch/powerpc/cpu/mpc83xx/bats/Kconfig"
source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig"
#ifndef CONFIG_DEFAULT_IMMR
#error CONFIG_DEFAULT_IMMR must be defined
#endif /* CONFIG_DEFAULT_IMMR */
-#ifndef CONFIG_SYS_IMMR
-#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
-#endif /* CONFIG_SYS_IMMR */
/*
* After configuration, a system reset exception is executed using the
help
Debug Event Register (37-47)
-config SYS_IMMR
- hex "Value for IMMR"
-
source "board/cssi/MCR3000/Kconfig"
endmenu
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="mcr3000"
CONFIG_MPC8xx=y
-CONFIG_SYS_IMMR=0xFF000000
CONFIG_TARGET_MCR3000=y
CONFIG_8xx_GCLK_FREQ=132000000
CONFIG_CMD_IMMAP=y
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_IDS8313=y
-CONFIG_SYS_IMMR=0xF0000000
CONFIG_CORE_PLL_RATIO_2_1=y
CONFIG_PCI_HOST_MODE_ENABLE=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_M68K
+#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
+#endif
+
#if !CONFIG_IS_ENABLED(DM_I2C)
static const struct fsl_i2c_base *i2c_base[4] = {
(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_UDP_CHECKSUM
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
#define CONFIG_HOSTNAME "M5253DEMO"
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
#define CONFIG_SYS_I2C_PINMUX_SET (0)
#endif
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
#define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_UDP_CHECKSUM
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_UDP_CHECKSUM
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_UDP_CHECKSUM
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/*
* Defines processor clock - important for correct timings concerning serial
* I2C
*/
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-
#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_DS1338
#define CONFIG_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
CONFIG_SYS_CCSRBAR_PHYS_LOW)
-#ifndef CONFIG_SYS_IMMR
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
-#endif
-
#endif /* __MPC85xx_H__ */