}
min_size = komeda_fb_get_pixel_addr(kfb, 0, fb->height, i)
- - to_drm_gem_dma_obj(obj)->paddr;
+ - to_drm_gem_dma_obj(obj)->dma_addr;
if (obj->size < min_size) {
DRM_DEBUG_KMS("The fb->obj[%d] size: 0x%zx lower than the minimum requirement: 0x%llx.\n",
i, obj->size, min_size);
+ plane_y * fb->pitches[plane];
}
- return obj->paddr + offset;
+ return obj->dma_addr + offset;
}
/* if the fb can be supported by a specific layer */
return -EINVAL;
}
mw_state->pitches[i] = fb->pitches[i];
- mw_state->addrs[i] = obj->paddr + fb->offsets[i];
+ mw_state->addrs[i] = obj->dma_addr + fb->offsets[i];
}
mw_state->n_planes = n_planes;
struct malidp_plane *mp,
int plane_index)
{
- dma_addr_t paddr;
+ dma_addr_t dma_addr;
u16 ptr;
struct drm_plane *plane = &mp->base;
bool afbc = fb->modifier ? true : false;
* and _AD_CROP_V registers.
*/
if (!afbc) {
- paddr = drm_fb_dma_get_gem_addr(fb, plane->state,
- plane_index);
+ dma_addr = drm_fb_dma_get_gem_addr(fb, plane->state,
+ plane_index);
} else {
struct drm_gem_dma_object *obj;
if (WARN_ON(!obj))
return;
- paddr = obj->paddr;
+ dma_addr = obj->dma_addr;
}
- malidp_hw_write(mp->hwdev, lower_32_bits(paddr), ptr);
- malidp_hw_write(mp->hwdev, upper_32_bits(paddr), ptr + 4);
+ malidp_hw_write(mp->hwdev, lower_32_bits(dma_addr), ptr);
+ malidp_hw_write(mp->hwdev, upper_32_bits(dma_addr), ptr + 4);
}
static void malidp_de_set_plane_afbc(struct drm_plane *plane)
gem = drm_fb_dma_get_gem_obj(fb, 0);
if (!gem)
return;
- writel(gem->paddr, priv->base + CRT_ADDR);
+ writel(gem->dma_addr, priv->base + CRT_ADDR);
}
static int aspeed_gfx_enable_vblank(struct drm_simple_display_pipe *pipe)
for (i = 0; i < state->nplanes; i++) {
struct drm_gem_dma_object *gem = drm_fb_dma_get_gem_obj(fb, i);
- state->dscrs[i]->addr = gem->paddr + state->offsets[i];
+ state->dscrs[i]->addr = gem->dma_addr + state->offsets[i];
atmel_hlcdc_layer_write_reg(&plane->layer,
ATMEL_HLCDC_LAYER_PLANE_HEAD(i),
unsigned int plane)
{
struct drm_gem_dma_object *obj;
- dma_addr_t paddr;
+ dma_addr_t dma_addr;
u8 h_div = 1, v_div = 1;
u32 block_w = drm_format_info_block_width(fb->format, plane);
u32 block_h = drm_format_info_block_height(fb->format, plane);
if (!obj)
return 0;
- paddr = obj->paddr + fb->offsets[plane];
+ dma_addr = obj->dma_addr + fb->offsets[plane];
if (plane > 0) {
h_div = fb->format->hsub;
block_start_y = (sample_y / block_h) * block_h;
num_hblocks = sample_x / block_w;
- paddr += fb->pitches[plane] * block_start_y;
- paddr += block_size * num_hblocks;
+ dma_addr += fb->pitches[plane] * block_start_y;
+ dma_addr += block_size * num_hblocks;
- return paddr;
+ return dma_addr;
}
EXPORT_SYMBOL_GPL(drm_fb_dma_get_gem_addr);
if (dma_obj->map_noncoherent) {
dma_obj->vaddr = dma_alloc_noncoherent(drm->dev, size,
- &dma_obj->paddr,
+ &dma_obj->dma_addr,
DMA_TO_DEVICE,
GFP_KERNEL | __GFP_NOWARN);
} else {
- dma_obj->vaddr = dma_alloc_wc(drm->dev, size, &dma_obj->paddr,
+ dma_obj->vaddr = dma_alloc_wc(drm->dev, size,
+ &dma_obj->dma_addr,
GFP_KERNEL | __GFP_NOWARN);
}
if (!dma_obj->vaddr) {
} else if (dma_obj->vaddr) {
if (dma_obj->map_noncoherent)
dma_free_noncoherent(gem_obj->dev->dev, dma_obj->base.size,
- dma_obj->vaddr, dma_obj->paddr,
+ dma_obj->vaddr, dma_obj->dma_addr,
DMA_TO_DEVICE);
else
dma_free_wc(gem_obj->dev->dev, dma_obj->base.size,
- dma_obj->vaddr, dma_obj->paddr);
+ dma_obj->vaddr, dma_obj->dma_addr);
}
drm_gem_object_release(gem_obj);
* @p: DRM printer
* @indent: Tab indentation level
*
- * This function prints paddr and vaddr for use in e.g. debugfs output.
+ * This function prints dma_addr and vaddr for use in e.g. debugfs output.
*/
void drm_gem_dma_print_info(const struct drm_gem_dma_object *dma_obj,
struct drm_printer *p, unsigned int indent)
{
- drm_printf_indent(p, indent, "paddr=%pad\n", &dma_obj->paddr);
+ drm_printf_indent(p, indent, "dma_addr=%pad\n", &dma_obj->dma_addr);
drm_printf_indent(p, indent, "vaddr=%p\n", dma_obj->vaddr);
}
EXPORT_SYMBOL(drm_gem_dma_print_info);
return ERR_PTR(-ENOMEM);
ret = dma_get_sgtable(obj->dev->dev, sgt, dma_obj->vaddr,
- dma_obj->paddr, obj->size);
+ dma_obj->dma_addr, obj->size);
if (ret < 0)
goto out;
if (IS_ERR(dma_obj))
return ERR_CAST(dma_obj);
- dma_obj->paddr = sg_dma_address(sgt->sgl);
+ dma_obj->dma_addr = sg_dma_address(sgt->sgl);
dma_obj->sgt = sgt;
- DRM_DEBUG_PRIME("dma_addr = %pad, size = %zu\n", &dma_obj->paddr, attach->dmabuf->size);
+ DRM_DEBUG_PRIME("dma_addr = %pad, size = %zu\n", &dma_obj->dma_addr,
+ attach->dmabuf->size);
return &dma_obj->base;
}
virt_to_page(dma_obj->vaddr));
} else {
ret = dma_mmap_wc(dma_obj->base.dev->dev, vma, dma_obj->vaddr,
- dma_obj->paddr, vma->vm_end - vma->vm_start);
+ dma_obj->dma_addr,
+ vma->vm_end - vma->vm_start);
}
if (ret)
drm_gem_vm_close(vma);
DCU_LAYER_POSY(new_state->crtc_y) |
DCU_LAYER_POSX(new_state->crtc_x));
regmap_write(fsl_dev->regmap,
- DCU_CTRLDESCLN(index, 3), gem->paddr);
+ DCU_CTRLDESCLN(index, 3), gem->dma_addr);
regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4),
DCU_LAYER_EN |
DCU_LAYER_TRANS(0xff) |
struct drm_gem_dma_object *obj = drm_fb_dma_get_gem_obj(fb, 0);
u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en;
u32 stride = fb->pitches[0];
- u32 addr = (u32)obj->paddr + y * stride;
+ u32 addr = (u32) obj->dma_addr + y * stride;
DRM_DEBUG_DRIVER("rdma%d: (y=%d, height=%d), stride=%d, paddr=0x%x\n",
- ch + 1, y, in_h, stride, (u32)obj->paddr);
+ ch + 1, y, in_h, stride, (u32) obj->dma_addr);
DRM_DEBUG_DRIVER("addr=0x%x, fb:%dx%d, pixel_format=%d(%p4cc)\n",
addr, fb->width, fb->height, fmt,
&fb->format->format);
if (!format->is_yuv ||
format->format == DRM_FORMAT_NV12 ||
format->format == DRM_FORMAT_NV21)
- p1_ba = dma_obj->paddr + fb->offsets[0] +
+ p1_ba = dma_obj->dma_addr + fb->offsets[0] +
fb->pitches[0] * (state->src.y1 >> 16) +
format->char_per_block[0] * (state->src.x1 >> 16);
else if (format->format == DRM_FORMAT_UYVY ||
format->format == DRM_FORMAT_VYUY ||
format->format == DRM_FORMAT_YUYV ||
format->format == DRM_FORMAT_YVYU)
- p1_ba = dma_obj->paddr + fb->offsets[0] +
+ p1_ba = dma_obj->dma_addr + fb->offsets[0] +
fb->pitches[0] * (state->src.y1 >> 16) +
2 * format->char_per_block[0] * (state->src.x1 >> 17);
if (format->format == DRM_FORMAT_NV12 ||
format->format == DRM_FORMAT_NV21)
- p2_ba = dma_obj->paddr + fb->offsets[1] +
+ p2_ba = dma_obj->dma_addr + fb->offsets[1] +
(((fb->pitches[1] >> 1) * (state->src.y1 >> 17) +
(state->src.x1 >> 17)) << 1);
dma_obj = drm_fb_dma_get_gem_obj(fb, plane);
BUG_ON(!dma_obj);
- return dma_obj->paddr + fb->offsets[plane] + fb->pitches[plane] * y +
+ return dma_obj->dma_addr + fb->offsets[plane] + fb->pitches[plane] * y +
fb->format->cpp[plane] * x;
}
x /= fb->format->hsub;
y /= fb->format->vsub;
- return dma_obj->paddr + fb->offsets[1] + fb->pitches[1] * y +
+ return dma_obj->dma_addr + fb->offsets[1] + fb->pitches[1] * y +
fb->format->cpp[1] * x - eba;
}
x /= fb->format->hsub;
y /= fb->format->vsub;
- return dma_obj->paddr + fb->offsets[2] + fb->pitches[2] * y +
+ return dma_obj->dma_addr + fb->offsets[2] + fb->pitches[2] * y +
fb->format->cpp[2] * x - eba;
}
switch (priv->viu.vd1_planes) {
case 3:
gem = drm_fb_dma_get_gem_obj(fb, 2);
- priv->viu.vd1_addr2 = gem->paddr + fb->offsets[2];
+ priv->viu.vd1_addr2 = gem->dma_addr + fb->offsets[2];
priv->viu.vd1_stride2 = fb->pitches[2];
priv->viu.vd1_height2 =
drm_format_info_plane_height(fb->format,
fallthrough;
case 2:
gem = drm_fb_dma_get_gem_obj(fb, 1);
- priv->viu.vd1_addr1 = gem->paddr + fb->offsets[1];
+ priv->viu.vd1_addr1 = gem->dma_addr + fb->offsets[1];
priv->viu.vd1_stride1 = fb->pitches[1];
priv->viu.vd1_height1 =
drm_format_info_plane_height(fb->format,
fallthrough;
case 1:
gem = drm_fb_dma_get_gem_obj(fb, 0);
- priv->viu.vd1_addr0 = gem->paddr + fb->offsets[0];
+ priv->viu.vd1_addr0 = gem->dma_addr + fb->offsets[0];
priv->viu.vd1_stride0 = fb->pitches[0];
priv->viu.vd1_height0 =
drm_format_info_plane_height(fb->format,
/* Update Canvas with buffer address */
gem = drm_fb_dma_get_gem_obj(fb, 0);
- priv->viu.osd1_addr = gem->paddr;
+ priv->viu.osd1_addr = gem->dma_addr;
priv->viu.osd1_stride = fb->pitches[0];
priv->viu.osd1_height = fb->height;
priv->viu.osd1_width = fb->width;
struct drm_bridge_state *bridge_state = NULL;
struct drm_device *drm = mxsfb->drm;
u32 bus_format = 0;
- dma_addr_t paddr;
+ dma_addr_t dma_addr;
pm_runtime_get_sync(drm->dev);
mxsfb_enable_axi_clk(mxsfb);
mxsfb_crtc_mode_set_nofb(mxsfb, bridge_state, bus_format);
/* Write cur_buf as well to avoid an initial corrupt frame */
- paddr = drm_fb_dma_get_gem_addr(new_pstate->fb, new_pstate, 0);
- if (paddr) {
- writel(paddr, mxsfb->base + mxsfb->devdata->cur_buf);
- writel(paddr, mxsfb->base + mxsfb->devdata->next_buf);
+ dma_addr = drm_fb_dma_get_gem_addr(new_pstate->fb, new_pstate, 0);
+ if (dma_addr) {
+ writel(dma_addr, mxsfb->base + mxsfb->devdata->cur_buf);
+ writel(dma_addr, mxsfb->base + mxsfb->devdata->next_buf);
}
mxsfb_enable_controller(mxsfb);
struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev);
struct drm_plane_state *new_pstate = drm_atomic_get_new_plane_state(state,
plane);
- dma_addr_t paddr;
+ dma_addr_t dma_addr;
- paddr = drm_fb_dma_get_gem_addr(new_pstate->fb, new_pstate, 0);
- if (paddr)
- writel(paddr, mxsfb->base + mxsfb->devdata->next_buf);
+ dma_addr = drm_fb_dma_get_gem_addr(new_pstate->fb, new_pstate, 0);
+ if (dma_addr)
+ writel(dma_addr, mxsfb->base + mxsfb->devdata->next_buf);
}
static void mxsfb_plane_overlay_atomic_update(struct drm_plane *plane,
struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev);
struct drm_plane_state *new_pstate = drm_atomic_get_new_plane_state(state,
plane);
- dma_addr_t paddr;
+ dma_addr_t dma_addr;
u32 ctrl;
- paddr = drm_fb_dma_get_gem_addr(new_pstate->fb, new_pstate, 0);
- if (!paddr) {
+ dma_addr = drm_fb_dma_get_gem_addr(new_pstate->fb, new_pstate, 0);
+ if (!dma_addr) {
writel(0, mxsfb->base + LCDC_AS_CTRL);
return;
}
* is understood, live with the 16 initial invalid pixels on the first
* line and start 64 bytes within the framebuffer.
*/
- paddr += 64;
+ dma_addr += 64;
- writel(paddr, mxsfb->base + LCDC_AS_NEXT_BUF);
+ writel(dma_addr, mxsfb->base + LCDC_AS_NEXT_BUF);
/*
* If the plane was previously disabled, write LCDC_AS_BUF as well to
* provide the first buffer.
*/
if (!old_pstate->fb)
- writel(paddr, mxsfb->base + LCDC_AS_BUF);
+ writel(dma_addr, mxsfb->base + LCDC_AS_BUF);
ctrl = AS_CTRL_AS_ENABLE | AS_CTRL_ALPHA(255);
return ERR_PTR(ret);
}
- dma_obj->paddr = 0;
+ dma_obj->dma_addr = 0;
dma_obj->sgt = sgt;
return gem_obj;
for (i = 0; i < state->format->planes; ++i) {
gem = drm_fb_dma_get_gem_obj(fb, i);
- dma[i] = gem->paddr + fb->offsets[i];
+ dma[i] = gem->dma_addr + fb->offsets[i];
}
} else {
pitch = drm_rect_width(&state->state.src) >> 16;
}
} else {
ret = dma_get_sgtable(rcdu->dev, sgt, gem->vaddr,
- gem->paddr, gem->base.size);
+ gem->dma_addr, gem->base.size);
if (ret)
goto fail;
}
bpp = scrtc->format->yuv ? 8 : scrtc->format->bpp;
gem = drm_fb_dma_get_gem_obj(fb, 0);
- scrtc->dma[0] = gem->paddr + fb->offsets[0]
+ scrtc->dma[0] = gem->dma_addr + fb->offsets[0]
+ y * fb->pitches[0] + x * bpp / 8;
if (scrtc->format->yuv) {
bpp = scrtc->format->bpp - 8;
gem = drm_fb_dma_get_gem_obj(fb, 1);
- scrtc->dma[1] = gem->paddr + fb->offsets[1]
+ scrtc->dma[1] = gem->dma_addr + fb->offsets[1]
+ y / (bpp == 4 ? 2 : 1) * fb->pitches[1]
+ x * (bpp == 16 ? 2 : 1);
}
bpp = splane->format->yuv ? 8 : splane->format->bpp;
gem = drm_fb_dma_get_gem_obj(fb, 0);
- splane->dma[0] = gem->paddr + fb->offsets[0]
+ splane->dma[0] = gem->dma_addr + fb->offsets[0]
+ y * fb->pitches[0] + x * bpp / 8;
if (splane->format->yuv) {
bpp = splane->format->bpp - 8;
gem = drm_fb_dma_get_gem_obj(fb, 1);
- splane->dma[1] = gem->paddr + fb->offsets[1]
+ splane->dma[1] = gem->dma_addr + fb->offsets[1]
+ y / (bpp == 4 ? 2 : 1) * fb->pitches[1]
+ x * (bpp == 16 ? 2 : 1);
}
for (i = 0; i < fb->format->num_planes; i++) {
dma_obj = drm_fb_dma_get_gem_obj(fb, i);
- addr = dma_obj->paddr + fb->offsets[i];
+ addr = dma_obj->dma_addr + fb->offsets[i];
if (i == 0)
layer_reg_wr(ctx, REG_LAY_BASE_ADDR0, addr, index);
DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id,
(char *)&fb->format->format,
- (unsigned long)dma_obj->paddr);
+ (unsigned long) dma_obj->dma_addr);
/* pixel memory location */
bpp = fb->format->cpp[0];
- top_field->gam_gdp_pml = (u32)dma_obj->paddr + fb->offsets[0];
+ top_field->gam_gdp_pml = (u32) dma_obj->dma_addr + fb->offsets[0];
top_field->gam_gdp_pml += src_x * bpp;
top_field->gam_gdp_pml += src_y * fb->pitches[0];
dev_dbg(gdp->dev, "Current NVN:0x%X\n",
readl(gdp->regs + GAM_GDP_NVN_OFFSET));
dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n",
- (unsigned long)dma_obj->paddr,
+ (unsigned long) dma_obj->dma_addr,
readl(gdp->regs + GAM_GDP_PML_OFFSET));
if (!curr_list) {
DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id,
(char *)&fb->format->format,
- (unsigned long)dma_obj->paddr);
+ (unsigned long) dma_obj->dma_addr);
/* Buffer planes address */
- cmd->top.current_luma = (u32)dma_obj->paddr + fb->offsets[0];
- cmd->top.current_chroma = (u32)dma_obj->paddr + fb->offsets[1];
+ cmd->top.current_luma = (u32) dma_obj->dma_addr + fb->offsets[0];
+ cmd->top.current_chroma = (u32) dma_obj->dma_addr + fb->offsets[1];
/* Pitches */
cmd->top.luma_processed_pitch = fb->pitches[0];
struct drm_plane_state *state = plane->state;
struct drm_framebuffer *fb = state->fb;
u32 lo_paddr, hi_paddr;
- dma_addr_t paddr;
+ dma_addr_t dma_addr;
/* Set the line width */
DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
fb->pitches[0] * 8);
/* Get the start of the displayed memory */
- paddr = drm_fb_dma_get_gem_addr(fb, state, 0);
- DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
+ dma_addr = drm_fb_dma_get_gem_addr(fb, state, 0);
+ DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &dma_addr);
if (fb->format->is_yuv)
- return sun4i_backend_update_yuv_buffer(backend, fb, paddr);
+ return sun4i_backend_update_yuv_buffer(backend, fb, dma_addr);
/* Write the 32 lower bits of the address (in bits) */
- lo_paddr = paddr << 3;
+ lo_paddr = dma_addr << 3;
DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr);
regmap_write(backend->engine.regs,
SUN4I_BACKEND_LAYFB_L32ADD_REG(layer),
lo_paddr);
/* And the upper bits */
- hi_paddr = paddr >> 29;
+ hi_paddr = dma_addr >> 29;
DRM_DEBUG_DRIVER("Setting address high bits to 0x%x\n", hi_paddr);
regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_LAYFB_H4ADD_REG,
SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer),
struct drm_framebuffer *fb = state->fb;
unsigned int strides[3] = {};
- dma_addr_t paddr;
+ dma_addr_t dma_addr;
bool swap;
if (fb->modifier == DRM_FORMAT_MOD_ALLWINNER_TILED) {
swap = sun4i_frontend_format_chroma_requires_swap(fb->format->format);
/* Set the physical address of the buffer in memory */
- paddr = drm_fb_dma_get_gem_addr(fb, state, 0);
- DRM_DEBUG_DRIVER("Setting buffer #0 address to %pad\n", &paddr);
- regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR0_REG, paddr);
+ dma_addr = drm_fb_dma_get_gem_addr(fb, state, 0);
+ DRM_DEBUG_DRIVER("Setting buffer #0 address to %pad\n", &dma_addr);
+ regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR0_REG, dma_addr);
if (fb->format->num_planes > 1) {
- paddr = drm_fb_dma_get_gem_addr(fb, state, swap ? 2 : 1);
- DRM_DEBUG_DRIVER("Setting buffer #1 address to %pad\n", &paddr);
+ dma_addr = drm_fb_dma_get_gem_addr(fb, state, swap ? 2 : 1);
+ DRM_DEBUG_DRIVER("Setting buffer #1 address to %pad\n",
+ &dma_addr);
regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR1_REG,
- paddr);
+ dma_addr);
}
if (fb->format->num_planes > 2) {
- paddr = drm_fb_dma_get_gem_addr(fb, state, swap ? 1 : 2);
- DRM_DEBUG_DRIVER("Setting buffer #2 address to %pad\n", &paddr);
+ dma_addr = drm_fb_dma_get_gem_addr(fb, state, swap ? 1 : 2);
+ DRM_DEBUG_DRIVER("Setting buffer #2 address to %pad\n",
+ &dma_addr);
regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR2_REG,
- paddr);
+ dma_addr);
}
}
EXPORT_SYMBOL(sun4i_frontend_update_buffer);
struct drm_plane_state *state = plane->state;
struct drm_framebuffer *fb = state->fb;
struct drm_gem_dma_object *gem;
- dma_addr_t paddr;
+ dma_addr_t dma_addr;
u32 ch_base;
int bpp;
/* Get the physical address of the buffer in memory */
gem = drm_fb_dma_get_gem_obj(fb, 0);
- DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
+ DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->dma_addr);
/* Compute the start of the displayed memory */
bpp = fb->format->cpp[0];
- paddr = gem->paddr + fb->offsets[0];
+ dma_addr = gem->dma_addr + fb->offsets[0];
/* Fixup framebuffer address for src coordinates */
- paddr += (state->src.x1 >> 16) * bpp;
- paddr += (state->src.y1 >> 16) * fb->pitches[0];
+ dma_addr += (state->src.x1 >> 16) * bpp;
+ dma_addr += (state->src.y1 >> 16) * fb->pitches[0];
/* Set the line width */
DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]);
SUN8I_MIXER_CHAN_UI_LAYER_PITCH(ch_base, overlay),
fb->pitches[0]);
- DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
+ DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &dma_addr);
regmap_write(mixer->engine.regs,
SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(ch_base, overlay),
- lower_32_bits(paddr));
+ lower_32_bits(dma_addr));
return 0;
}
const struct drm_format_info *format = fb->format;
struct drm_gem_dma_object *gem;
u32 dx, dy, src_x, src_y;
- dma_addr_t paddr;
+ dma_addr_t dma_addr;
u32 ch_base;
int i;
/* Get the physical address of the buffer in memory */
gem = drm_fb_dma_get_gem_obj(fb, i);
- DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
+ DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->dma_addr);
/* Compute the start of the displayed memory */
- paddr = gem->paddr + fb->offsets[i];
+ dma_addr = gem->dma_addr + fb->offsets[i];
dx = src_x;
dy = src_y;
}
/* Fixup framebuffer address for src coordinates */
- paddr += dx * format->cpp[i];
- paddr += dy * fb->pitches[i];
+ dma_addr += dx * format->cpp[i];
+ dma_addr += dy * fb->pitches[i];
/* Set the line width */
DRM_DEBUG_DRIVER("Layer %d. line width: %d bytes\n",
fb->pitches[i]);
DRM_DEBUG_DRIVER("Setting %d. buffer address to %pad\n",
- i + 1, &paddr);
+ i + 1, &dma_addr);
regmap_write(mixer->engine.regs,
SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(ch_base,
overlay, i),
- lower_32_bits(paddr));
+ lower_32_bits(dma_addr));
}
return 0;
}
static
-dma_addr_t dispc_plane_state_paddr(const struct drm_plane_state *state)
+dma_addr_t dispc_plane_state_dma_addr(const struct drm_plane_state *state)
{
struct drm_framebuffer *fb = state->fb;
struct drm_gem_dma_object *gem;
gem = drm_fb_dma_get_gem_obj(state->fb, 0);
- return gem->paddr + fb->offsets[0] + x * fb->format->cpp[0] +
+ return gem->dma_addr + fb->offsets[0] + x * fb->format->cpp[0] +
y * fb->pitches[0];
}
gem = drm_fb_dma_get_gem_obj(fb, 1);
- return gem->paddr + fb->offsets[1] +
+ return gem->dma_addr + fb->offsets[1] +
(x * fb->format->cpp[1] / fb->format->hsub) +
(y * fb->pitches[1] / fb->format->vsub);
}
u32 fourcc = state->fb->format->format;
u16 cpp = state->fb->format->cpp[0];
u32 fb_width = state->fb->pitches[0] / cpp;
- dma_addr_t paddr = dispc_plane_state_paddr(state);
+ dma_addr_t dma_addr = dispc_plane_state_dma_addr(state);
struct dispc_scaling_params scale;
dispc_vid_calc_scaling(dispc, state, &scale, lite);
dispc_plane_set_pixel_format(dispc, hw_plane, fourcc);
- dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, paddr & 0xffffffff);
- dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)paddr >> 32);
- dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, paddr & 0xffffffff);
- dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)paddr >> 32);
+ dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, dma_addr & 0xffffffff);
+ dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32);
+ dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff);
+ dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32);
dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE,
(scale.in_w - 1) | ((scale.in_h - 1) << 16));
gem = drm_fb_dma_get_gem_obj(fb, 0);
- start = gem->paddr + fb->offsets[0] +
+ start = gem->dma_addr + fb->offsets[0] +
crtc->y * fb->pitches[0] +
crtc->x * fb->format->cpp[0];
arcpgu = pipe_to_arcpgu_priv(pipe);
gem = drm_fb_dma_get_gem_obj(pipe->plane.state->fb, 0);
- arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
+ arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->dma_addr);
}
static const struct drm_simple_display_pipe_funcs arc_pgu_pipe_funcs = {
drm_vma_node_unmap(&obj->vma_node, dev->anon_inode->i_mapping);
- dma_free_wc(dev->dev, obj->size, bo->base.vaddr, bo->base.paddr);
+ dma_free_wc(dev->dev, obj->size, bo->base.vaddr, bo->base.dma_addr);
bo->base.vaddr = NULL;
bo->madv = __VC4_MADV_PURGED;
}
goto err_delete_handle;
}
bo_state[i].handle = handle;
- bo_state[i].paddr = vc4_bo->base.paddr;
+ bo_state[i].paddr = vc4_bo->base.dma_addr;
bo_state[i].size = vc4_bo->base.base.size;
}
list_add_tail(&to_vc4_bo(&exec->exec_bo->base)->unref_head,
&exec->unref_list);
- exec->ct0ca = exec->exec_bo->paddr + bin_offset;
+ exec->ct0ca = exec->exec_bo->dma_addr + bin_offset;
exec->bin_u = bin;
exec->shader_rec_v = exec->exec_bo->vaddr + shader_rec_offset;
- exec->shader_rec_p = exec->exec_bo->paddr + shader_rec_offset;
+ exec->shader_rec_p = exec->exec_bo->dma_addr + shader_rec_offset;
exec->shader_rec_size = args->shader_rec_size;
exec->uniforms_v = exec->exec_bo->vaddr + uniforms_offset;
- exec->uniforms_p = exec->exec_bo->paddr + uniforms_offset;
+ exec->uniforms_p = exec->exec_bo->dma_addr + uniforms_offset;
exec->uniforms_size = args->uniforms_size;
ret = vc4_validate_bin_cl(dev,
}
vc4->bin_alloc_overflow = BIT(bin_bo_slot);
- V3D_WRITE(V3D_BPOA, bo->base.paddr + bin_bo_slot * vc4->bin_alloc_size);
+ V3D_WRITE(V3D_BPOA, bo->base.dma_addr + bin_bo_slot * vc4->bin_alloc_size);
V3D_WRITE(V3D_BPOS, bo->base.base.size);
V3D_WRITE(V3D_INTCTL, V3D_INT_OUTOMEM);
V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM);
return ret;
for (i = 0; i < num_planes; i++)
- vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
+ vc4_state->offsets[i] = bo->dma_addr + fb->offsets[i];
/*
* We don't support subpixel source positioning for scaling,
* because this is only called on the primary plane.
*/
WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0);
- addr = bo->paddr + fb->offsets[0];
+ addr = bo->dma_addr + fb->offsets[0];
/* Write the new address into the hardware immediately. The
* scanout will start from this address as soon as the FIFO
struct drm_vc4_submit_rcl_surface *surf,
uint8_t x, uint8_t y)
{
- return bo->paddr + surf->offset + VC4_TILE_BUFFER_SIZE *
+ return bo->dma_addr + surf->offset + VC4_TILE_BUFFER_SIZE *
(DIV_ROUND_UP(exec->args->width, 32) * y + x);
}
} else {
rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
rcl_u16(setup, args->color_read.bits);
- rcl_u32(setup, setup->color_read->paddr +
+ rcl_u32(setup, setup->color_read->dma_addr +
args->color_read.offset);
}
}
} else {
rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
rcl_u16(setup, args->zs_read.bits);
- rcl_u32(setup, setup->zs_read->paddr +
+ rcl_u32(setup, setup->zs_read->dma_addr +
args->zs_read.offset);
}
}
(last_tile_write ?
0 : VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR));
rcl_u32(setup,
- (setup->zs_write->paddr + args->zs_write.offset) |
+ (setup->zs_write->dma_addr + args->zs_write.offset) |
((last && last_tile_write) ?
VC4_LOADSTORE_TILE_BUFFER_EOF : 0));
}
rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
rcl_u32(setup,
- (setup->color_write ? (setup->color_write->paddr +
+ (setup->color_write ? (setup->color_write->dma_addr +
args->color_write.offset) :
0));
rcl_u16(setup, args->width);
}
BUG_ON(setup->next_offset != size);
- exec->ct1ca = setup->rcl->paddr;
- exec->ct1ea = setup->rcl->paddr + setup->next_offset;
+ exec->ct1ca = setup->rcl->dma_addr;
+ exec->ct1ea = setup->rcl->dma_addr + setup->next_offset;
return 0;
}
return;
gem = drm_fb_dma_get_gem_obj(fb, 0);
- TXP_WRITE(TXP_DST_PTR, gem->paddr + fb->offsets[0]);
+ TXP_WRITE(TXP_DST_PTR, gem->dma_addr + fb->offsets[0]);
TXP_WRITE(TXP_DST_PITCH, fb->pitches[0]);
TXP_WRITE(TXP_DIM,
VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) |
}
/* Check if this BO won't trigger the addressing bug. */
- if ((bo->base.paddr & 0xf0000000) ==
- ((bo->base.paddr + bo->base.base.size - 1) & 0xf0000000)) {
+ if ((bo->base.dma_addr & 0xf0000000) ==
+ ((bo->base.dma_addr + bo->base.base.size - 1) & 0xf0000000)) {
vc4->bin_bo = bo;
/* Set up for allocating 512KB chunks of
return -EINVAL;
}
- *(uint32_t *)(validated + 5) = ib->paddr + offset;
+ *(uint32_t *)(validated + 5) = ib->dma_addr + offset;
return 0;
}
* free when the job completes rendering.
*/
exec->bin_slots |= BIT(bin_slot);
- bin_addr = vc4->bin_bo->base.paddr + bin_slot * vc4->bin_alloc_size;
+ bin_addr = vc4->bin_bo->base.dma_addr + bin_slot * vc4->bin_alloc_size;
/* The tile state data array is 48 bytes per tile, and we put it at
* the start of a BO containing both it and the tile alloc.
"outside of UBO\n");
goto fail;
}
- *validated_p0 = tex->paddr + p0;
+ *validated_p0 = tex->dma_addr + p0;
return true;
}
offset -= level_size;
}
- *validated_p0 = tex->paddr + p0;
+ *validated_p0 = tex->dma_addr + p0;
if (is_cs) {
exec->bin_dep_seqno = max(exec->bin_dep_seqno,
void *uniform_data_u;
uint32_t tex, uni;
- *(uint32_t *)(pkt_v + o) = bo[i]->paddr + src_offset;
+ *(uint32_t *)(pkt_v + o) = bo[i]->dma_addr + src_offset;
if (src_offset != 0) {
DRM_DEBUG("Shaders must be at offset 0 of "
}
}
- *(uint32_t *)(pkt_v + o) = vbo->paddr + offset;
+ *(uint32_t *)(pkt_v + o) = vbo->dma_addr + offset;
}
return 0;
unsigned int height = state->crtc_h / (i ? info->vsub : 1);
struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
struct dma_async_tx_descriptor *desc;
- dma_addr_t paddr;
+ dma_addr_t dma_addr;
- paddr = drm_fb_dma_get_gem_addr(state->fb, state, i);
+ dma_addr = drm_fb_dma_get_gem_addr(state->fb, state, i);
dma->xt.numf = height;
dma->sgl.size = width * info->cpp[i];
dma->sgl.icg = state->fb->pitches[i] - dma->sgl.size;
- dma->xt.src_start = paddr;
+ dma->xt.src_start = dma_addr;
dma->xt.frame_size = 1;
dma->xt.dir = DMA_MEM_TO_DEV;
dma->xt.src_sgl = true;
/**
* struct drm_gem_dma_object - GEM object backed by DMA memory allocations
* @base: base GEM object
- * @paddr: DMA address of the backing memory
+ * @dma_addr: DMA address of the backing memory
* @sgt: scatter/gather table for imported PRIME buffers. The table can have
* more than one entry but they are guaranteed to have contiguous
* DMA addresses.
*/
struct drm_gem_dma_object {
struct drm_gem_object base;
- dma_addr_t paddr;
+ dma_addr_t dma_addr;
struct sg_table *sgt;
/* For objects with DMA memory allocated by GEM DMA */
projects / kernel.git / commitdiff