refactor(tc): update total compute gpu device node

updated gpu clocks and added gpu simple power model node

Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ia475f136bec8a569f764255eb87c212a692626dc

diff --git a/fdts/tc.dts b/fdts/tc.dts
index 192f407c3284f305bddd24efdce0f3a727ee3b19..3836dc59f689d672c4cbacc17c7870ca17098c8f 100644 (file)
--- a/fdts/tc.dts
+++ b/fdts/tc.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -456,13 +456,25 @@
                clock-names = "mclk", "apb_pclk";
        };
 
+       gpu_clk: gpu_clk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <1000000000>;
+       };
+
+       gpu_core_clk: gpu_core_clk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <1000000000>;
+       };
+
        gpu: gpu@2d000000 {
                compatible = "arm,mali-midgard";
                reg = <0x0 0x2d000000 0x0 0x200000>;
                interrupts = <0 66 4>, <0 67 4>, <0 65 4>;
                interrupt-names = "JOB", "MMU", "GPU";
-               clocks = <&soc_refclk100mhz>;
-               clock-names = "clk_mali";
+               clocks = <&gpu_clk>, <&gpu_core_clk>;
+               clock-names = "clk_mali", "shadercores";
                iommus = <&smmu_700 0x200>;
                operating-points = <
                        /* KHz uV */
@@ -470,6 +482,18 @@
                >;
        };
 
+       power_model@simple {
+               /*
+                * Numbers used are irrelevant to Titan,
+                * it helps suppressing the kernel warnings.
+                */
+               compatible = "arm,mali-simple-power-model";
+               static-coefficient = <2427750>;
+               dynamic-coefficient = <4687>;
+               ts = <20000 2000 (-20) 2>;
+               thermal-zone = "";
+       };
+
        smmu_700: smmu_700@3f000000 {
                #iommu-cells = <1>;
                compatible = "arm,smmu-v3";