refactor(xilinx): move enum to common place

Moved IOCTL enum from ZynqMP to common place so that it can be used
for all the platforms.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I6ad992da30f2def9f46c8ba79753d79ed00fe024

diff --git a/plat/xilinx/common/include/pm_defs.h b/plat/xilinx/common/include/pm_defs.h
index 09507dda5f271d05baf0253a4f7198041a544551..0188443342eb1d3281a592c170ffb54094d04b49 100644 (file)
--- a/plat/xilinx/common/include/pm_defs.h
+++ b/plat/xilinx/common/include/pm_defs.h
@@ -46,13 +46,6 @@
 #define PM_LOAD_PDI                    0x701U
 #define PM_LOAD_GET_HANDOFF_PARAMS     0x70BU
 
-/* IOCTL IDs for clock driver */
-#define IOCTL_SET_PLL_FRAC_MODE                8U
-#define        IOCTL_GET_PLL_FRAC_MODE         9U
-#define        IOCTL_SET_PLL_FRAC_DATA         10U
-#define        IOCTL_GET_PLL_FRAC_DATA         11U
-#define        IOCTL_SET_SGI                   25U
-
 /* System shutdown macros */
 #define        XPM_SHUTDOWN_TYPE_SHUTDOWN      0U
 #define        XPM_SHUTDOWN_TYPE_RESET         1U
@@ -66,6 +59,44 @@
  * Enum definitions
  ********************************************************************/
 
+//ioctl id
+enum {
+       IOCTL_GET_RPU_OPER_MODE = 0,
+       IOCTL_SET_RPU_OPER_MODE = 1,
+       IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
+       IOCTL_TCM_COMB_CONFIG = 3,
+       IOCTL_SET_TAPDELAY_BYPASS = 4,
+       IOCTL_SET_SGMII_MODE = 5,
+       IOCTL_SD_DLL_RESET = 6,
+       IOCTL_SET_SD_TAPDELAY = 7,
+        /* Ioctl for clock driver */
+       IOCTL_SET_PLL_FRAC_MODE = 8,
+       IOCTL_GET_PLL_FRAC_MODE = 9,
+       IOCTL_SET_PLL_FRAC_DATA = 10,
+       IOCTL_GET_PLL_FRAC_DATA = 11,
+       IOCTL_WRITE_GGS = 12,
+       IOCTL_READ_GGS = 13,
+       IOCTL_WRITE_PGGS = 14,
+       IOCTL_READ_PGGS = 15,
+       /* IOCTL for ULPI reset */
+       IOCTL_ULPI_RESET = 16,
+       /* Set healthy bit value */
+       IOCTL_SET_BOOT_HEALTH_STATUS = 17,
+       IOCTL_AFI = 18,
+       /* Probe counter read/write */
+       IOCTL_PROBE_COUNTER_READ = 19,
+       IOCTL_PROBE_COUNTER_WRITE = 20,
+       IOCTL_OSPI_MUX_SELECT = 21,
+       /* IOCTL for USB power request */
+       IOCTL_USB_SET_STATE = 22,
+       /* IOCTL to get last reset reason */
+       IOCTL_GET_LAST_RESET_REASON = 23,
+       /* AI engine NPI ISR clear */
+       IOCTL_AIE_ISR_CLEAR = 24,
+       /* Register SGI to TF-A */
+       IOCTL_SET_SGI = 25,
+};
+
 /**
  * @PM_PLL_PARAM_DIV2:         Enable for divide by 2 function inside the PLL
  * @PM_PLL_PARAM_FBDIV:                Feedback divisor integer portion for the PLL

diff --git a/plat/xilinx/versal_net/include/plat_private.h b/plat/xilinx/versal_net/include/plat_private.h
index fc4a6fdd88749596eb6ccc11ae561ccead4e4989..ca4ed1d95b130acc2342cc4298c16f4b68c44483 100644 (file)
--- a/plat/xilinx/versal_net/include/plat_private.h
+++ b/plat/xilinx/versal_net/include/plat_private.h
@@ -43,6 +43,4 @@ int32_t sip_svc_setup_init(void);
  */
 int request_intr_type_el3(uint32_t irq, interrupt_type_handler_t fiq_handler);
 
-#define IOCTL_OSPI_MUX_SELECT          (21U)
-
 #endif /* PLAT_PRIVATE_H */

diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
index 3b0d6ee37ea249bffd81a9c72bdcd4942b521956..de93b2d7adfd823ce47ad4987190c123df9f1a88 100644 (file)
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,44 +14,6 @@
 
 #include "pm_common.h"
 
-//ioctl id
-enum {
-       IOCTL_GET_RPU_OPER_MODE = 0,
-       IOCTL_SET_RPU_OPER_MODE = 1,
-       IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
-       IOCTL_TCM_COMB_CONFIG = 3,
-       IOCTL_SET_TAPDELAY_BYPASS = 4,
-       IOCTL_SET_SGMII_MODE = 5,
-       IOCTL_SD_DLL_RESET = 6,
-       IOCTL_SET_SD_TAPDELAY = 7,
-        /* Ioctl for clock driver */
-       IOCTL_SET_PLL_FRAC_MODE = 8,
-       IOCTL_GET_PLL_FRAC_MODE = 9,
-       IOCTL_SET_PLL_FRAC_DATA = 10,
-       IOCTL_GET_PLL_FRAC_DATA = 11,
-       IOCTL_WRITE_GGS = 12,
-       IOCTL_READ_GGS = 13,
-       IOCTL_WRITE_PGGS = 14,
-       IOCTL_READ_PGGS = 15,
-       /* IOCTL for ULPI reset */
-       IOCTL_ULPI_RESET = 16,
-       /* Set healthy bit value */
-       IOCTL_SET_BOOT_HEALTH_STATUS = 17,
-       IOCTL_AFI = 18,
-       /* Probe counter read/write */
-       IOCTL_PROBE_COUNTER_READ = 19,
-       IOCTL_PROBE_COUNTER_WRITE = 20,
-       IOCTL_OSPI_MUX_SELECT = 21,
-       /* IOCTL for USB power request */
-       IOCTL_USB_SET_STATE = 22,
-       /* IOCTL to get last reset reason */
-       IOCTL_GET_LAST_RESET_REASON = 23,
-       /* AI engine NPI ISR clear */
-       IOCTL_AIE_ISR_CLEAR = 24,
-       /* Register SGI to ATF */
-       IOCTL_REGISTER_SGI = 25,
-};
-
 //RPU operation mode
 #define        PM_RPU_MODE_LOCKSTEP 0U
 #define        PM_RPU_MODE_SPLIT 1U