fix(cpus): workaround for Cortex-X3 erratum 2615812

Cortex-X3 erratum 2615812 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1, and is still open. The workaround is to disable
the use of the Full Retention power mode in the core (setting
WFI_RET_CTRL and WFE_RET_CTRL in CORTEX_X3_IMP_CPUPWRCTLR_EL1 to 0b000).

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2055130/latest

Change-Id: I5ad66df3e18fc85a6b23f6662239494ee001d82f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 55e265c9ab32ef49e957bccb532fb29514c7390c..d48f284fb70052a9fe6658e19b4f964802c85600 100644 (file)
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -601,6 +601,10 @@ For Cortex-X3, the following errata build flags are defined :
   Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0
   of the CPU, it is fixed in r1p1.
 
+- ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3
+  CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
+  CPU, it is still open.
+
 For Cortex-A510, the following errata build flags are defined :
 
 -  ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to

diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h
index 076a87b3524bab634256473d71bb21a7489ae388..ceafe6647093bb2d917ac1ef7fb1c68665d58128 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_x3.h
+++ b/include/lib/cpus/aarch64/cortex_x3.h
@@ -10,7 +10,7 @@
 #define CORTEX_X3_MIDR                         U(0x410FD4E0)
 
 /* Cortex-X3 loop count for CVE-2022-23960 mitigation */
-#define CORTEX_X3_BHB_LOOP_COUNT                       U(132)
+#define CORTEX_X3_BHB_LOOP_COUNT               U(132)
 
 /*******************************************************************************
  * CPU Extended Control register specific definitions
@@ -20,8 +20,10 @@
 /*******************************************************************************
  * CPU Power Control register specific definitions
  ******************************************************************************/
-#define CORTEX_X3_CPUPWRCTLR_EL1                       S3_0_C15_C2_7
-#define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT        U(1)
+#define CORTEX_X3_CPUPWRCTLR_EL1                               S3_0_C15_C2_7
+#define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT                        U(1)
+#define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT       U(4)
+#define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT       U(7)
 
 /*******************************************************************************
  * CPU Auxiliary Control register 2 specific definitions.

diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index bf1b6ec4a3ede27d32e702b9dc0575b36cc7b58e..f104b487f8d74108b4d38ad25b1c958153b16561 100644 (file)
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -59,6 +59,7 @@ func check_errata_cve_2022_23960
 endfunc check_errata_cve_2022_23960
 
 func cortex_x3_reset_func
+       mov     x19, x30
        /* Disable speculative loads */
        msr     SSBS, xzr
 
@@ -71,8 +72,14 @@ func cortex_x3_reset_func
        msr     vbar_el3, x0
 #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
 
+       bl      cpu_get_rev_var
+
+#if ERRATA_X3_2615812
+       bl      errata_cortex_x3_2615812_wa
+#endif /* ERRATA_X3_2615812 */
+
        isb
-       ret
+       ret     x19
 endfunc cortex_x3_reset_func
 
 /* ----------------------------------------------------------------------
@@ -103,6 +110,35 @@ func check_errata_2313909
        b       cpu_rev_var_ls
 endfunc check_errata_2313909
 
+/* ----------------------------------------------------------------------
+ * Errata Workaround for Cortex-X3 Erratum 2615812 on power-on.
+ * This applies to revision r0p0, r1p0, r1p1 of Cortex-X3. Open.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x1, x17
+ * ----------------------------------------------------------------------
+ */
+func errata_cortex_x3_2615812_wa
+       /* Check revision. */
+       mov     x17, x30
+       bl      check_errata_2615812
+       cbz     x0, 1f
+
+       /* Disable retention control for WFI and WFE. */
+       mrs     x0, CORTEX_X3_CPUPWRCTLR_EL1
+       bfi     x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3
+       bfi     x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3
+       msr     CORTEX_X3_CPUPWRCTLR_EL1, x0
+1:
+       ret     x17
+endfunc errata_cortex_x3_2615812_wa
+
+func check_errata_2615812
+       /* Applies to r1p1 and below. */
+       mov     x1, #0x11
+       b       cpu_rev_var_ls
+endfunc check_errata_2615812
+
 #if REPORT_ERRATA
        /*
         * Errata printing function for Cortex-X3. Must follow AAPCS.
@@ -118,6 +154,7 @@ func cortex_x3_errata_report
         * checking functions of each errata.
         */
        report_errata ERRATA_X3_2313909, cortex_x3, 2313909
+       report_errata ERRATA_X3_2615812, cortex_x3, 2615812
        report_errata WORKAROUND_CVE_2022_23960, cortex_x3, cve_2022_23960
 
        ldp     x8, x30, [sp], #16

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index f19c16e49fd61be2a63355b07011610e910e2ca1..8ef794b4571d3333621d578d94bf97c345937956 100644 (file)
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -659,6 +659,10 @@ ERRATA_X2_2371105  ?=0
 # to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1.
 ERRATA_X3_2313909      ?=0
 
+# Flag to apply erratum 2615812 workaround on powerdown. This erratum applies
+# to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is still open.
+ERRATA_X3_2615812      ?=0
+
 # Flag to apply erratum 1922240 workaround during reset. This erratum applies
 # to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
 ERRATA_A510_1922240    ?=0
@@ -1288,6 +1292,10 @@ $(eval $(call add_define,ERRATA_X2_2371105))
 $(eval $(call assert_boolean,ERRATA_X3_2313909))
 $(eval $(call add_define,ERRATA_X3_2313909))
 
+# Process ERRATA_X3_2615812 flag
+$(eval $(call assert_boolean,ERRATA_X3_2615812))
+$(eval $(call add_define,ERRATA_X3_2615812))
+
 # Process ERRATA_A510_1922240 flag
 $(eval $(call assert_boolean,ERRATA_A510_1922240))
 $(eval $(call add_define,ERRATA_A510_1922240))