mlxsw: Configure egress FID classification after routing

After routing, a packet needs to perform an L2 lookup using the DMAC it got
from the routing and a FID. In unified bridge model, the egress FID
configuration needs to be performed by software.

It is configured by RITR for both sub-port RIFs and FID RIFs. Currently
FID RIFs already configure eFID. Add eFID configuration for sub-port RIFs.

Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h
index 46ed2c1810becd4f9631c457ea7d77e2ec819792..520b990054eb4fe48ddfa006e44b841d2eb85c13 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h
@@ -7113,10 +7113,11 @@ static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
 }
 
 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
-                                            u16 system_port, u16 vid)
+                                            u16 system_port, u16 efid, u16 vid)
 {
        mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
        mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
+       mlxsw_reg_ritr_sp_if_efid_set(payload, efid);
        mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
 }
 

diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c
index fe3ae524f340d3990661f4285532e2eb66d7a787..eec4fb0561e942d3878d6ab6e8eb8a7231709a17 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c
@@ -9316,15 +9316,18 @@ static int mlxsw_sp_rif_subport_op(struct mlxsw_sp_rif *rif, bool enable)
        struct mlxsw_sp *mlxsw_sp = rif->mlxsw_sp;
        struct mlxsw_sp_rif_subport *rif_subport;
        char ritr_pl[MLXSW_REG_RITR_LEN];
+       u16 efid;
 
        rif_subport = mlxsw_sp_rif_subport_rif(rif);
        mlxsw_reg_ritr_pack(ritr_pl, enable, MLXSW_REG_RITR_SP_IF,
                            rif->rif_index, rif->vr_id, rif->dev->mtu);
        mlxsw_reg_ritr_mac_pack(ritr_pl, rif->dev->dev_addr);
        mlxsw_reg_ritr_if_mac_profile_id_set(ritr_pl, rif->mac_profile_id);
+       efid = mlxsw_sp->ubridge ? mlxsw_sp_fid_index(rif->fid) : 0;
        mlxsw_reg_ritr_sp_if_pack(ritr_pl, rif_subport->lag,
                                  rif_subport->lag ? rif_subport->lag_id :
                                                     rif_subport->system_port,
+                                 efid,
                                  mlxsw_sp->ubridge ? 0 : rif_subport->vid);
 
        return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);