drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result

Not sure what that should originally been good for, but it doesn't seem
to make any sense any more.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index a296f7bbe57cbb0c768499a6c254e433d931773a..8ba056a2a5da9ede328b0bc5541d0b745b445df6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -757,72 +757,72 @@ static void cik_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_BONAIRE:
                amdgpu_program_register_sequence(adev,
                                                 bonaire_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
+                                                ARRAY_SIZE(bonaire_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 bonaire_golden_registers,
-                                                (const u32)ARRAY_SIZE(bonaire_golden_registers));
+                                                ARRAY_SIZE(bonaire_golden_registers));
                amdgpu_program_register_sequence(adev,
                                                 bonaire_golden_common_registers,
-                                                (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
+                                                ARRAY_SIZE(bonaire_golden_common_registers));
                amdgpu_program_register_sequence(adev,
                                                 bonaire_golden_spm_registers,
-                                                (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
+                                                ARRAY_SIZE(bonaire_golden_spm_registers));
                break;
        case CHIP_KABINI:
                amdgpu_program_register_sequence(adev,
                                                 kalindi_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
+                                                ARRAY_SIZE(kalindi_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 kalindi_golden_registers,
-                                                (const u32)ARRAY_SIZE(kalindi_golden_registers));
+                                                ARRAY_SIZE(kalindi_golden_registers));
                amdgpu_program_register_sequence(adev,
                                                 kalindi_golden_common_registers,
-                                                (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
+                                                ARRAY_SIZE(kalindi_golden_common_registers));
                amdgpu_program_register_sequence(adev,
                                                 kalindi_golden_spm_registers,
-                                                (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
+                                                ARRAY_SIZE(kalindi_golden_spm_registers));
                break;
        case CHIP_MULLINS:
                amdgpu_program_register_sequence(adev,
                                                 kalindi_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
+                                                ARRAY_SIZE(kalindi_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 godavari_golden_registers,
-                                                (const u32)ARRAY_SIZE(godavari_golden_registers));
+                                                ARRAY_SIZE(godavari_golden_registers));
                amdgpu_program_register_sequence(adev,
                                                 kalindi_golden_common_registers,
-                                                (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
+                                                ARRAY_SIZE(kalindi_golden_common_registers));
                amdgpu_program_register_sequence(adev,
                                                 kalindi_golden_spm_registers,
-                                                (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
+                                                ARRAY_SIZE(kalindi_golden_spm_registers));
                break;
        case CHIP_KAVERI:
                amdgpu_program_register_sequence(adev,
                                                 spectre_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
+                                                ARRAY_SIZE(spectre_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 spectre_golden_registers,
-                                                (const u32)ARRAY_SIZE(spectre_golden_registers));
+                                                ARRAY_SIZE(spectre_golden_registers));
                amdgpu_program_register_sequence(adev,
                                                 spectre_golden_common_registers,
-                                                (const u32)ARRAY_SIZE(spectre_golden_common_registers));
+                                                ARRAY_SIZE(spectre_golden_common_registers));
                amdgpu_program_register_sequence(adev,
                                                 spectre_golden_spm_registers,
-                                                (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
+                                                ARRAY_SIZE(spectre_golden_spm_registers));
                break;
        case CHIP_HAWAII:
                amdgpu_program_register_sequence(adev,
                                                 hawaii_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
+                                                ARRAY_SIZE(hawaii_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 hawaii_golden_registers,
-                                                (const u32)ARRAY_SIZE(hawaii_golden_registers));
+                                                ARRAY_SIZE(hawaii_golden_registers));
                amdgpu_program_register_sequence(adev,
                                                 hawaii_golden_common_registers,
-                                                (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
+                                                ARRAY_SIZE(hawaii_golden_common_registers));
                amdgpu_program_register_sequence(adev,
                                                 hawaii_golden_spm_registers,
-                                                (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
+                                                ARRAY_SIZE(hawaii_golden_spm_registers));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index f3dd6b7bfd4d559e5edbff230e7c7194f22431ef..a397111c2cedb9d34aa2d4de292af9bbe19e3499 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -147,18 +147,18 @@ static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_FIJI:
                amdgpu_program_register_sequence(adev,
                                                 fiji_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
+                                                ARRAY_SIZE(fiji_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_fiji_a10,
-                                                (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
+                                                ARRAY_SIZE(golden_settings_fiji_a10));
                break;
        case CHIP_TONGA:
                amdgpu_program_register_sequence(adev,
                                                 tonga_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
+                                                ARRAY_SIZE(tonga_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_tonga_a11,
-                                                (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
+                                                ARRAY_SIZE(golden_settings_tonga_a11));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index be25706e5f07f1581fafe7b4499ead63e23dadcd..67e670989e81539e9de3ceac09a4d2be99a22407 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -156,26 +156,26 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_CARRIZO:
                amdgpu_program_register_sequence(adev,
                                                 cz_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
+                                                ARRAY_SIZE(cz_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 cz_golden_settings_a11,
-                                                (const u32)ARRAY_SIZE(cz_golden_settings_a11));
+                                                ARRAY_SIZE(cz_golden_settings_a11));
                break;
        case CHIP_STONEY:
                amdgpu_program_register_sequence(adev,
                                                 stoney_golden_settings_a11,
-                                                (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
+                                                ARRAY_SIZE(stoney_golden_settings_a11));
                break;
        case CHIP_POLARIS11:
        case CHIP_POLARIS12:
                amdgpu_program_register_sequence(adev,
                                                 polaris11_golden_settings_a11,
-                                                (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
+                                                ARRAY_SIZE(polaris11_golden_settings_a11));
                break;
        case CHIP_POLARIS10:
                amdgpu_program_register_sequence(adev,
                                                 polaris10_golden_settings_a11,
-                                                (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
+                                                ARRAY_SIZE(polaris10_golden_settings_a11));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 96a3345e872e82f15caf9b289706b3aac7c892ff..426e51866a156b97a316c5a13f0f3b60a07513ca 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -681,53 +681,53 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_TOPAZ:
                amdgpu_program_register_sequence(adev,
                                                 iceland_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
+                                                ARRAY_SIZE(iceland_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_iceland_a11,
-                                                (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
+                                                ARRAY_SIZE(golden_settings_iceland_a11));
                amdgpu_program_register_sequence(adev,
                                                 iceland_golden_common_all,
-                                                (const u32)ARRAY_SIZE(iceland_golden_common_all));
+                                                ARRAY_SIZE(iceland_golden_common_all));
                break;
        case CHIP_FIJI:
                amdgpu_program_register_sequence(adev,
                                                 fiji_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
+                                                ARRAY_SIZE(fiji_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_fiji_a10,
-                                                (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
+                                                ARRAY_SIZE(golden_settings_fiji_a10));
                amdgpu_program_register_sequence(adev,
                                                 fiji_golden_common_all,
-                                                (const u32)ARRAY_SIZE(fiji_golden_common_all));
+                                                ARRAY_SIZE(fiji_golden_common_all));
                break;
 
        case CHIP_TONGA:
                amdgpu_program_register_sequence(adev,
                                                 tonga_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
+                                                ARRAY_SIZE(tonga_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_tonga_a11,
-                                                (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
+                                                ARRAY_SIZE(golden_settings_tonga_a11));
                amdgpu_program_register_sequence(adev,
                                                 tonga_golden_common_all,
-                                                (const u32)ARRAY_SIZE(tonga_golden_common_all));
+                                                ARRAY_SIZE(tonga_golden_common_all));
                break;
        case CHIP_POLARIS11:
        case CHIP_POLARIS12:
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_polaris11_a11,
-                                                (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
+                                                ARRAY_SIZE(golden_settings_polaris11_a11));
                amdgpu_program_register_sequence(adev,
                                                 polaris11_golden_common_all,
-                                                (const u32)ARRAY_SIZE(polaris11_golden_common_all));
+                                                ARRAY_SIZE(polaris11_golden_common_all));
                break;
        case CHIP_POLARIS10:
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_polaris10_a11,
-                                                (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
+                                                ARRAY_SIZE(golden_settings_polaris10_a11));
                amdgpu_program_register_sequence(adev,
                                                 polaris10_golden_common_all,
-                                                (const u32)ARRAY_SIZE(polaris10_golden_common_all));
+                                                ARRAY_SIZE(polaris10_golden_common_all));
                WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
                if (adev->pdev->revision == 0xc7 &&
                    ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
@@ -740,24 +740,24 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_CARRIZO:
                amdgpu_program_register_sequence(adev,
                                                 cz_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
+                                                ARRAY_SIZE(cz_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 cz_golden_settings_a11,
-                                                (const u32)ARRAY_SIZE(cz_golden_settings_a11));
+                                                ARRAY_SIZE(cz_golden_settings_a11));
                amdgpu_program_register_sequence(adev,
                                                 cz_golden_common_all,
-                                                (const u32)ARRAY_SIZE(cz_golden_common_all));
+                                                ARRAY_SIZE(cz_golden_common_all));
                break;
        case CHIP_STONEY:
                amdgpu_program_register_sequence(adev,
                                                 stoney_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
+                                                ARRAY_SIZE(stoney_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 stoney_golden_settings_a11,
-                                                (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
+                                                ARRAY_SIZE(stoney_golden_settings_a11));
                amdgpu_program_register_sequence(adev,
                                                 stoney_golden_common_all,
-                                                (const u32)ARRAY_SIZE(stoney_golden_common_all));
+                                                ARRAY_SIZE(stoney_golden_common_all));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 19a619f759f6dbfd67a06b0fd56a63155c9b2231..5ba24792f80153890212e44db8e31af93605c0d6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -232,18 +232,18 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_VEGA10:
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_gc_9_0,
-                                                (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
+                                                ARRAY_SIZE(golden_settings_gc_9_0));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_gc_9_0_vg10,
-                                                (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
+                                                ARRAY_SIZE(golden_settings_gc_9_0_vg10));
                break;
        case CHIP_RAVEN:
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_gc_9_1,
-                                                (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
+                                                ARRAY_SIZE(golden_settings_gc_9_1));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_gc_9_1_rv1,
-                                                (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
+                                                ARRAY_SIZE(golden_settings_gc_9_1_rv1));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 583d87792820aba418ef6bf43e8207ee30872959..6c6a7e14359c7e6f816af2ca25b5cf817f50fbc1 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -69,10 +69,10 @@ static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_TOPAZ:
                amdgpu_program_register_sequence(adev,
                                                 iceland_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
+                                                ARRAY_SIZE(iceland_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_iceland_a11,
-                                                (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
+                                                ARRAY_SIZE(golden_settings_iceland_a11));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 9ca5fea93ebc71b7980b01d9e3634df88ff90d20..edbe0df24d903424faf09312c3b4b498e5b91dc3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -122,42 +122,42 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_FIJI:
                amdgpu_program_register_sequence(adev,
                                                 fiji_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
+                                                ARRAY_SIZE(fiji_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_fiji_a10,
-                                                (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
+                                                ARRAY_SIZE(golden_settings_fiji_a10));
                break;
        case CHIP_TONGA:
                amdgpu_program_register_sequence(adev,
                                                 tonga_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
+                                                ARRAY_SIZE(tonga_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_tonga_a11,
-                                                (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
+                                                ARRAY_SIZE(golden_settings_tonga_a11));
                break;
        case CHIP_POLARIS11:
        case CHIP_POLARIS12:
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_polaris11_a11,
-                                                (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
+                                                ARRAY_SIZE(golden_settings_polaris11_a11));
                break;
        case CHIP_POLARIS10:
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_polaris10_a11,
-                                                (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
+                                                ARRAY_SIZE(golden_settings_polaris10_a11));
                break;
        case CHIP_CARRIZO:
                amdgpu_program_register_sequence(adev,
                                                 cz_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
+                                                ARRAY_SIZE(cz_mgcg_cgcg_init));
                break;
        case CHIP_STONEY:
                amdgpu_program_register_sequence(adev,
                                                 stoney_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
+                                                ARRAY_SIZE(stoney_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_stoney_common,
-                                                (const u32)ARRAY_SIZE(golden_settings_stoney_common));
+                                                ARRAY_SIZE(golden_settings_stoney_common));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index f11dfd47b5176fff0809c50e09487cc7575fb1bd..69c9af7af6f4accf2746eeb6418f06b6aaca93a9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -696,15 +696,15 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_VEGA10:
                amdgpu_program_register_sequence(adev,
                                                golden_settings_mmhub_1_0_0,
-                                               (const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0));
+                                               ARRAY_SIZE(golden_settings_mmhub_1_0_0));
                amdgpu_program_register_sequence(adev,
                                                golden_settings_athub_1_0_0,
-                                               (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
+                                               ARRAY_SIZE(golden_settings_athub_1_0_0));
                break;
        case CHIP_RAVEN:
                amdgpu_program_register_sequence(adev,
                                                golden_settings_athub_1_0_0,
-                                               (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
+                                               ARRAY_SIZE(golden_settings_athub_1_0_0));
                break;
        default:
                break;
@@ -724,7 +724,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
 
        amdgpu_program_register_sequence(adev,
                golden_settings_vega10_hdp,
-               (const u32)ARRAY_SIZE(golden_settings_vega10_hdp));
+               ARRAY_SIZE(golden_settings_vega10_hdp));
 
        if (adev->gart.robj == NULL) {
                dev_err(adev->dev, "No VRAM object for PCIE GART.\n");

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index 2b435c02ef447e4cc035e0b038c83d922dd56cc8..df52824c0cd416154251847b247b4ef638c99c03 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -281,29 +281,29 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_FIJI:
                amdgpu_program_register_sequence(adev,
                                                 xgpu_fiji_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(
+                                                ARRAY_SIZE(
                                                 xgpu_fiji_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 xgpu_fiji_golden_settings_a10,
-                                                (const u32)ARRAY_SIZE(
+                                                ARRAY_SIZE(
                                                 xgpu_fiji_golden_settings_a10));
                amdgpu_program_register_sequence(adev,
                                                 xgpu_fiji_golden_common_all,
-                                                (const u32)ARRAY_SIZE(
+                                                ARRAY_SIZE(
                                                 xgpu_fiji_golden_common_all));
                break;
        case CHIP_TONGA:
                amdgpu_program_register_sequence(adev,
                                                 xgpu_tonga_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(
+                                                ARRAY_SIZE(
                                                 xgpu_tonga_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 xgpu_tonga_golden_settings_a11,
-                                                (const u32)ARRAY_SIZE(
+                                                ARRAY_SIZE(
                                                 xgpu_tonga_golden_settings_a11));
                amdgpu_program_register_sequence(adev,
                                                 xgpu_tonga_golden_common_all,
-                                                (const u32)ARRAY_SIZE(
+                                                ARRAY_SIZE(
                                                 xgpu_tonga_golden_common_all));
                break;
        default:

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 92f8c44a73b6df68a97c129c17f3c8aa6b20cc7d..121e628e7cdb0ee16902733994f501d491ef539f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -95,10 +95,10 @@ static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_TOPAZ:
                amdgpu_program_register_sequence(adev,
                                                 iceland_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
+                                                ARRAY_SIZE(iceland_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_iceland_a11,
-                                                (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
+                                                ARRAY_SIZE(golden_settings_iceland_a11));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 52e6bf2e9e595ad569fa0a01aa5fdd550cfbd983..c8c93f9dac2143c2fdbf49a0087eb55271f49cb4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -194,45 +194,45 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_FIJI:
                amdgpu_program_register_sequence(adev,
                                                 fiji_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
+                                                ARRAY_SIZE(fiji_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_fiji_a10,
-                                                (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
+                                                ARRAY_SIZE(golden_settings_fiji_a10));
                break;
        case CHIP_TONGA:
                amdgpu_program_register_sequence(adev,
                                                 tonga_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
+                                                ARRAY_SIZE(tonga_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_tonga_a11,
-                                                (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
+                                                ARRAY_SIZE(golden_settings_tonga_a11));
                break;
        case CHIP_POLARIS11:
        case CHIP_POLARIS12:
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_polaris11_a11,
-                                                (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
+                                                ARRAY_SIZE(golden_settings_polaris11_a11));
                break;
        case CHIP_POLARIS10:
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_polaris10_a11,
-                                                (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
+                                                ARRAY_SIZE(golden_settings_polaris10_a11));
                break;
        case CHIP_CARRIZO:
                amdgpu_program_register_sequence(adev,
                                                 cz_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
+                                                ARRAY_SIZE(cz_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 cz_golden_settings_a11,
-                                                (const u32)ARRAY_SIZE(cz_golden_settings_a11));
+                                                ARRAY_SIZE(cz_golden_settings_a11));
                break;
        case CHIP_STONEY:
                amdgpu_program_register_sequence(adev,
                                                 stoney_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
+                                                ARRAY_SIZE(stoney_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 stoney_golden_settings_a11,
-                                                (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
+                                                ARRAY_SIZE(stoney_golden_settings_a11));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index fe78c00b9ffa793df52709ccd5cf58533eaa8e51..a0a5a8da4c4f746f86123f1c398273aafd7d3cf3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -132,18 +132,18 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_VEGA10:
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_sdma_4,
-                                                (const u32)ARRAY_SIZE(golden_settings_sdma_4));
+                                                ARRAY_SIZE(golden_settings_sdma_4));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_sdma_vg10,
-                                                (const u32)ARRAY_SIZE(golden_settings_sdma_vg10));
+                                                ARRAY_SIZE(golden_settings_sdma_vg10));
                break;
        case CHIP_RAVEN:
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_sdma_4_1,
-                                                (const u32)ARRAY_SIZE(golden_settings_sdma_4_1));
+                                                ARRAY_SIZE(golden_settings_sdma_4_1));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_sdma_rv1,
-                                                (const u32)ARRAY_SIZE(golden_settings_sdma_rv1));
+                                                ARRAY_SIZE(golden_settings_sdma_rv1));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 8284d5dbfc30c5227088de36d269459e3c3511b8..49eef3090f085013e51ba6fcafcf75cb7ee0eecc 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1392,63 +1392,63 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_TAHITI:
                amdgpu_program_register_sequence(adev,
                                                 tahiti_golden_registers,
-                                                (const u32)ARRAY_SIZE(tahiti_golden_registers));
+                                                ARRAY_SIZE(tahiti_golden_registers));
                amdgpu_program_register_sequence(adev,
                                                 tahiti_golden_rlc_registers,
-                                                (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
+                                                ARRAY_SIZE(tahiti_golden_rlc_registers));
                amdgpu_program_register_sequence(adev,
                                                 tahiti_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
+                                                ARRAY_SIZE(tahiti_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 tahiti_golden_registers2,
-                                                (const u32)ARRAY_SIZE(tahiti_golden_registers2));
+                                                ARRAY_SIZE(tahiti_golden_registers2));
                break;
        case CHIP_PITCAIRN:
                amdgpu_program_register_sequence(adev,
                                                 pitcairn_golden_registers,
-                                                (const u32)ARRAY_SIZE(pitcairn_golden_registers));
+                                                ARRAY_SIZE(pitcairn_golden_registers));
                amdgpu_program_register_sequence(adev,
                                                 pitcairn_golden_rlc_registers,
-                                                (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
+                                                ARRAY_SIZE(pitcairn_golden_rlc_registers));
                amdgpu_program_register_sequence(adev,
                                                 pitcairn_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
+                                                ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
                break;
        case CHIP_VERDE:
                amdgpu_program_register_sequence(adev,
                                                 verde_golden_registers,
-                                                (const u32)ARRAY_SIZE(verde_golden_registers));
+                                                ARRAY_SIZE(verde_golden_registers));
                amdgpu_program_register_sequence(adev,
                                                 verde_golden_rlc_registers,
-                                                (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
+                                                ARRAY_SIZE(verde_golden_rlc_registers));
                amdgpu_program_register_sequence(adev,
                                                 verde_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
+                                                ARRAY_SIZE(verde_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 verde_pg_init,
-                                                (const u32)ARRAY_SIZE(verde_pg_init));
+                                                ARRAY_SIZE(verde_pg_init));
                break;
        case CHIP_OLAND:
                amdgpu_program_register_sequence(adev,
                                                 oland_golden_registers,
-                                                (const u32)ARRAY_SIZE(oland_golden_registers));
+                                                ARRAY_SIZE(oland_golden_registers));
                amdgpu_program_register_sequence(adev,
                                                 oland_golden_rlc_registers,
-                                                (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
+                                                ARRAY_SIZE(oland_golden_rlc_registers));
                amdgpu_program_register_sequence(adev,
                                                 oland_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
+                                                ARRAY_SIZE(oland_mgcg_cgcg_init));
                break;
        case CHIP_HAINAN:
                amdgpu_program_register_sequence(adev,
                                                 hainan_golden_registers,
-                                                (const u32)ARRAY_SIZE(hainan_golden_registers));
+                                                ARRAY_SIZE(hainan_golden_registers));
                amdgpu_program_register_sequence(adev,
                                                 hainan_golden_registers2,
-                                                (const u32)ARRAY_SIZE(hainan_golden_registers2));
+                                                ARRAY_SIZE(hainan_golden_registers2));
                amdgpu_program_register_sequence(adev,
                                                 hainan_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
+                                                ARRAY_SIZE(hainan_mgcg_cgcg_init));
                break;
 
 

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 4e67fe1e79553d610c79819b525ecb881c13d059..fa27e0354f3569cd42552774e74dc46aa94cc332 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -265,12 +265,12 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_VEGA10:
                amdgpu_program_register_sequence(adev,
                                                 vega10_golden_init,
-                                                (const u32)ARRAY_SIZE(vega10_golden_init));
+                                                ARRAY_SIZE(vega10_golden_init));
                break;
        case CHIP_RAVEN:
                amdgpu_program_register_sequence(adev,
                                                 raven_golden_init,
-                                                (const u32)ARRAY_SIZE(raven_golden_init));
+                                                ARRAY_SIZE(raven_golden_init));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 3a4c2fa7e36dbcf258f9a54c851828951e203f62..bb8ca9489546aed8be038d8c67dd86b388289cd0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -284,27 +284,27 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
        case CHIP_TOPAZ:
                amdgpu_program_register_sequence(adev,
                                                 iceland_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
+                                                ARRAY_SIZE(iceland_mgcg_cgcg_init));
                break;
        case CHIP_FIJI:
                amdgpu_program_register_sequence(adev,
                                                 fiji_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
+                                                ARRAY_SIZE(fiji_mgcg_cgcg_init));
                break;
        case CHIP_TONGA:
                amdgpu_program_register_sequence(adev,
                                                 tonga_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
+                                                ARRAY_SIZE(tonga_mgcg_cgcg_init));
                break;
        case CHIP_CARRIZO:
                amdgpu_program_register_sequence(adev,
                                                 cz_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
+                                                ARRAY_SIZE(cz_mgcg_cgcg_init));
                break;
        case CHIP_STONEY:
                amdgpu_program_register_sequence(adev,
                                                 stoney_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
+                                                ARRAY_SIZE(stoney_mgcg_cgcg_init));
                break;
        case CHIP_POLARIS11:
        case CHIP_POLARIS10: