riscv: dts: microchip: add the sundance polarberry

Add a minimal device tree for the PolarFire SoC based Sundance
PolarBerry.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220509142610.128590-9-conor.dooley@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index af3a5059b35002d6949fe03b30d4778138cb5cc8..39aae7b04f1cba08cef29b4c0f4475815d330847 100644 (file)
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
 obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
new file mode 100644 (file)
index 0000000..49380c4
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2022 Microchip Technology Inc */
+
+/ {
+       fabric_clk3: fabric-clk3 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <62500000>;
+       };
+
+       fabric_clk1: fabric-clk1 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <125000000>;
+       };
+};

diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
new file mode 100644 (file)
index 0000000..82c93c8
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2022 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-polarberry-fabric.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define MTIMER_FREQ    1000000
+
+/ {
+       model = "Sundance PolarBerry";
+       compatible = "sundance,polarberry", "microchip,mpfs";
+
+       aliases {
+               ethernet0 = &mac1;
+               serial0 = &mmuart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       cpus {
+               timebase-frequency = <MTIMER_FREQ>;
+       };
+
+       ddrc_cache_lo: memory@80000000 {
+               device_type = "memory";
+               reg = <0x0 0x80000000 0x0 0x2e000000>;
+       };
+
+       ddrc_cache_hi: memory@1000000000 {
+               device_type = "memory";
+               reg = <0x10 0x00000000 0x0 0xC0000000>;
+       };
+};
+
+/*
+ * phy0 is connected to mac0, but the port itself is on the (optional) carrier
+ * board.
+ */
+&mac0 {
+       phy-mode = "sgmii";
+       phy-handle = <&phy0>;
+       status = "disabled";
+};
+
+&mac1 {
+       phy-mode = "sgmii";
+       phy-handle = <&phy1>;
+       status = "okay";
+
+       phy1: ethernet-phy@5 {
+               reg = <5>;
+               ti,fifo-depth = <0x01>;
+       };
+
+       phy0: ethernet-phy@4 {
+               reg = <4>;
+               ti,fifo-depth = <0x01>;
+       };
+};
+
+&mbox {
+       status = "okay";
+};
+
+&mmc {
+       bus-width = <4>;
+       disable-wp;
+       cap-sd-highspeed;
+       cap-mmc-highspeed;
+       card-detect-delay = <200>;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+       sd-uhs-sdr12;
+       sd-uhs-sdr25;
+       sd-uhs-sdr50;
+       sd-uhs-sdr104;
+       status = "okay";
+};
+
+&mmuart0 {
+       status = "okay";
+};
+
+&refclk {
+       clock-frequency = <125000000>;
+};
+
+&rtc {
+       status = "okay";
+};
+
+&syscontroller {
+       status = "okay";
+};