refactor(st): move GIC code to common directory

The GIC v2 initialization code could be shared to other ST platforms.
The stm32mp1_gic.c file is then moved to common directory, and renamed
stm32mp_gic.c.
The functions are also prefixed with stm32mp_gic.

Change-Id: I60820823b470217d3a95cc569f941c2cb923dfa9
Signed-off-by: Yann Gautier <yann.gautier@st.com>

diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index 54cfcfb2f4000b045e2cfc1b52dc6b1a637c9918..1d592bd9dd25a50d5a00dd4430ea9dc70fa567ca 100644 (file)
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -35,6 +35,9 @@ uintptr_t stm32mp_pwr_base(void);
 /* Return the base address of the RCC peripheral */
 uintptr_t stm32mp_rcc_base(void);
 
+void stm32mp_gic_pcpu_init(void);
+void stm32mp_gic_init(void);
+
 /* Check MMU status to allow spinlock use */
 bool stm32mp_lock_available(void);
 

diff --git a/plat/st/common/stm32mp_gic.c b/plat/st/common/stm32mp_gic.c
new file mode 100644 (file)
index 0000000..d02b635
--- /dev/null
+++ b/plat/st/common/stm32mp_gic.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <drivers/arm/gicv2.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <lib/utils.h>
+#include <libfdt.h>
+#include <plat/common/platform.h>
+
+#include <platform_def.h>
+
+struct stm32mp_gic_instance {
+       uint32_t cells;
+       uint32_t phandle_node;
+};
+
+/******************************************************************************
+ * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
+ * interrupts.
+ *****************************************************************************/
+static const interrupt_prop_t stm32mp_interrupt_props[] = {
+       PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
+       PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
+};
+
+/* Fix target_mask_array as secondary core is not able to initialize it */
+static unsigned int target_mask_array[PLATFORM_CORE_COUNT] = {1, 2};
+
+static gicv2_driver_data_t platform_gic_data = {
+       .interrupt_props = stm32mp_interrupt_props,
+       .interrupt_props_num = ARRAY_SIZE(stm32mp_interrupt_props),
+       .target_masks = target_mask_array,
+       .target_masks_num = ARRAY_SIZE(target_mask_array),
+};
+
+static struct stm32mp_gic_instance stm32mp_gic;
+
+void stm32mp_gic_init(void)
+{
+       int node;
+       void *fdt;
+       const fdt32_t *cuint;
+       struct dt_node_info dt_gic;
+
+       if (fdt_get_address(&fdt) == 0) {
+               panic();
+       }
+
+       node = dt_get_node(&dt_gic, -1, "arm,cortex-a7-gic");
+       if (node < 0) {
+               panic();
+       }
+
+       platform_gic_data.gicd_base = dt_gic.base;
+
+       cuint = fdt_getprop(fdt, node, "reg", NULL);
+       if (cuint == NULL) {
+               panic();
+       }
+
+       platform_gic_data.gicc_base = fdt32_to_cpu(*(cuint + 2));
+
+       cuint = fdt_getprop(fdt, node, "#interrupt-cells", NULL);
+       if (cuint == NULL) {
+               panic();
+       }
+
+       stm32mp_gic.cells = fdt32_to_cpu(*cuint);
+
+       stm32mp_gic.phandle_node = fdt_get_phandle(fdt, node);
+       if (stm32mp_gic.phandle_node == 0U) {
+               panic();
+       }
+
+       gicv2_driver_init(&platform_gic_data);
+       gicv2_distif_init();
+
+       stm32mp_gic_pcpu_init();
+}
+
+void stm32mp_gic_pcpu_init(void)
+{
+       gicv2_pcpu_distif_init();
+       gicv2_set_pe_target_mask(plat_my_core_pos());
+       gicv2_cpuif_enable();
+}

diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h
index 21ef60d0a839c411acaf3985809e1f2f8550c239..4a522555dab22af198ed1496f9053ad85de2b642 100644 (file)
--- a/plat/st/stm32mp1/include/stm32mp1_private.h
+++ b/plat/st/stm32mp1/include/stm32mp1_private.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,9 +14,6 @@ void configure_mmu(void);
 void stm32mp1_arch_security_setup(void);
 void stm32mp1_security_setup(void);
 
-void stm32mp1_gic_pcpu_init(void);
-void stm32mp1_gic_init(void);
-
 void stm32mp1_syscfg_init(void);
 void stm32mp1_syscfg_enable_io_compensation_start(void);
 void stm32mp1_syscfg_enable_io_compensation_finish(void);

diff --git a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
index 1d754d98083fe08a2aab7bc97bf39a4b384128f8..f5184e7491131113305dc98a8b563a0703e2d7b3 100644 (file)
--- a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
+++ b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -32,7 +32,7 @@ include drivers/arm/gic/v2/gicv2.mk
 
 BL32_SOURCES           +=      ${GICV2_SOURCES}                        \
                                plat/common/plat_gicv2.c                \
-                               plat/st/stm32mp1/stm32mp1_gic.c
+                               plat/st/common/stm32mp_gic.c
 
 # Generic PSCI
 BL32_SOURCES           +=      plat/common/plat_psci_common.c

diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c
index 50b079471dc415a2b59ff53446ed5330ef745dab..b46f4af44eacba97f49d09799fb3c7301bdf5bfa 100644 (file)
--- a/plat/st/stm32mp1/sp_min/sp_min_setup.c
+++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,9 +7,8 @@
 #include <assert.h>
 #include <string.h>
 
-#include <platform_def.h>
-
 #include <arch_helpers.h>
+#include <bl32/sp_min/platform_sp_min.h>
 #include <common/bl_common.h>
 #include <common/debug.h>
 #include <context.h>
@@ -27,7 +26,7 @@
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/platform.h>
 
-#include <platform_sp_min.h>
+#include <platform_def.h>
 
 /******************************************************************************
  * Placeholder variables for copying the arguments that have been passed to
@@ -181,7 +180,7 @@ void sp_min_platform_setup(void)
 {
        generic_delay_timer_init();
 
-       stm32mp1_gic_init();
+       stm32mp_gic_init();
 
        if (stm32_iwdg_init() < 0) {
                panic();

diff --git a/plat/st/stm32mp1/stm32mp1_gic.c b/plat/st/stm32mp1/stm32mp1_gic.c
deleted file mode 100644 (file)
index 851a9cf..0000000
--- a/plat/st/stm32mp1/stm32mp1_gic.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <libfdt.h>
-
-#include <platform_def.h>
-
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <drivers/arm/gicv2.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <lib/utils.h>
-#include <plat/common/platform.h>
-
-struct stm32_gic_instance {
-       uint32_t cells;
-       uint32_t phandle_node;
-};
-
-/******************************************************************************
- * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
- * interrupts.
- *****************************************************************************/
-static const interrupt_prop_t stm32mp1_interrupt_props[] = {
-       PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
-       PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
-};
-
-/* Fix target_mask_array as secondary core is not able to initialize it */
-static unsigned int target_mask_array[PLATFORM_CORE_COUNT] = {1, 2};
-
-static gicv2_driver_data_t platform_gic_data = {
-       .interrupt_props = stm32mp1_interrupt_props,
-       .interrupt_props_num = ARRAY_SIZE(stm32mp1_interrupt_props),
-       .target_masks = target_mask_array,
-       .target_masks_num = ARRAY_SIZE(target_mask_array),
-};
-
-static struct stm32_gic_instance stm32_gic;
-
-void stm32mp1_gic_init(void)
-{
-       int node;
-       void *fdt;
-       const fdt32_t *cuint;
-       struct dt_node_info dt_gic;
-
-       if (fdt_get_address(&fdt) == 0) {
-               panic();
-       }
-
-       node = dt_get_node(&dt_gic, -1, "arm,cortex-a7-gic");
-       if (node < 0) {
-               panic();
-       }
-
-       platform_gic_data.gicd_base = dt_gic.base;
-
-       cuint = fdt_getprop(fdt, node, "reg", NULL);
-       if (cuint == NULL) {
-               panic();
-       }
-
-       platform_gic_data.gicc_base = fdt32_to_cpu(*(cuint + 2));
-
-       cuint = fdt_getprop(fdt, node, "#interrupt-cells", NULL);
-       if (cuint == NULL) {
-               panic();
-       }
-
-       stm32_gic.cells = fdt32_to_cpu(*cuint);
-
-       stm32_gic.phandle_node = fdt_get_phandle(fdt, node);
-       if (stm32_gic.phandle_node == 0U) {
-               panic();
-       }
-
-       gicv2_driver_init(&platform_gic_data);
-       gicv2_distif_init();
-
-       stm32mp1_gic_pcpu_init();
-}
-
-void stm32mp1_gic_pcpu_init(void)
-{
-       gicv2_pcpu_distif_init();
-       gicv2_set_pe_target_mask(plat_my_core_pos());
-       gicv2_cpuif_enable();
-}

diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c
index 6e438c44e96948cb061029678046121d7469b3d7..74393811ce01fe398f1c093304337b24c03419c4 100644 (file)
--- a/plat/st/stm32mp1/stm32mp1_pm.c
+++ b/plat/st/stm32mp1/stm32mp1_pm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -118,7 +118,7 @@ static void stm32_pwr_domain_suspend(const psci_power_state_t *target_state)
  ******************************************************************************/
 static void stm32_pwr_domain_on_finish(const psci_power_state_t *target_state)
 {
-       stm32mp1_gic_pcpu_init();
+       stm32mp_gic_pcpu_init();
 
        write_cntfrq_el0(cntfrq_core0);
 }