video: atmel: Drop pre-DM parts of video driver

This relies on the old LCD implementation which is to be removed. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 64e086cd2768c0c93e75149080d47dac6af1b44f..b537b367761ab9154280a1014023627b3f10ef8a 100644 (file)
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -430,7 +430,7 @@ config VIDEO_LCD_ANX9804
 
 config ATMEL_LCD
        bool "Atmel LCD panel support"
-       depends on LCD && ARCH_AT91
+       depends on DM_VIDEO && ARCH_AT91
 
 config ATMEL_LCD_BGR555
        bool "Display in BGR555 mode"
@@ -585,6 +585,7 @@ config NXP_TDA19988
 
 config ATMEL_HLCD
        bool "Enable ATMEL video support using HLCDC"
+       depends on DM_VIDEO
        help
           HLCDC supports video output to an attached LCD panel.
 

diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c
index caf65741f2e9a2e543fb5ef894da1bb8d0e06ba5..6e6704c141e5c9f9a1d1723cf1dc37fb73f39de9 100644 (file)
--- a/drivers/video/atmel_hlcdfb.c
+++ b/drivers/video/atmel_hlcdfb.c
@@ -25,217 +25,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_DM_VIDEO
-
-/* configurable parameters */
-#define ATMEL_LCDC_CVAL_DEFAULT                0xc8
-#define ATMEL_LCDC_DMA_BURST_LEN       8
-#ifndef ATMEL_LCDC_GUARD_TIME
-#define ATMEL_LCDC_GUARD_TIME          1
-#endif
-
-#define ATMEL_LCDC_FIFO_SIZE           512
-
-/*
- * the CLUT register map as following
- * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
- */
-void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
-{
-       writel(panel_info.mmio + ATMEL_LCDC_LUT(regno),
-              ((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
-              | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
-              | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk));
-}
-
-void lcd_ctrl_init(void *lcdbase)
-{
-       unsigned long value;
-       struct lcd_dma_desc *desc;
-       struct atmel_hlcd_regs *regs;
-       int ret;
-
-       if (!has_lcdc())
-               return;     /* No lcdc */
-
-       regs = (struct atmel_hlcd_regs *)panel_info.mmio;
-
-       /* Disable DISP signal */
-       writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
-       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
-                               false, 1000, false);
-       if (ret)
-               printf("%s: %d: Timeout!\n", __func__, __LINE__);
-       /* Disable synchronization */
-       writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
-       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
-                               false, 1000, false);
-       if (ret)
-               printf("%s: %d: Timeout!\n", __func__, __LINE__);
-       /* Disable pixel clock */
-       writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
-       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
-                               false, 1000, false);
-       if (ret)
-               printf("%s: %d: Timeout!\n", __func__, __LINE__);
-       /* Disable PWM */
-       writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
-       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
-                               false, 1000, false);
-       if (ret)
-               printf("%s: %d: Timeout!\n", __func__, __LINE__);
-
-       /* Set pixel clock */
-       value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
-       if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
-               value++;
-
-       if (value < 1) {
-               /* Using system clock as pixel clock */
-               writel(LCDC_LCDCFG0_CLKDIV(0)
-                       | LCDC_LCDCFG0_CGDISHCR
-                       | LCDC_LCDCFG0_CGDISHEO
-                       | LCDC_LCDCFG0_CGDISOVR1
-                       | LCDC_LCDCFG0_CGDISBASE
-                       | panel_info.vl_clk_pol
-                       | LCDC_LCDCFG0_CLKSEL,
-                       &regs->lcdc_lcdcfg0);
-
-       } else {
-               writel(LCDC_LCDCFG0_CLKDIV(value - 2)
-                       | LCDC_LCDCFG0_CGDISHCR
-                       | LCDC_LCDCFG0_CGDISHEO
-                       | LCDC_LCDCFG0_CGDISOVR1
-                       | LCDC_LCDCFG0_CGDISBASE
-                       | panel_info.vl_clk_pol,
-                       &regs->lcdc_lcdcfg0);
-       }
-
-       /* Initialize control register 5 */
-       value = 0;
-
-       value |= panel_info.vl_sync;
-
-#ifndef LCD_OUTPUT_BPP
-       /* Output is 24bpp */
-       value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
-#else
-       switch (LCD_OUTPUT_BPP) {
-       case 12:
-               value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
-               break;
-       case 16:
-               value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
-               break;
-       case 18:
-               value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
-               break;
-       case 24:
-               value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
-               break;
-       default:
-               BUG();
-               break;
-       }
-#endif
-
-       value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
-       value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
-       writel(value, &regs->lcdc_lcdcfg5);
-
-       /* Vertical & Horizontal Timing */
-       value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
-       value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
-       writel(value, &regs->lcdc_lcdcfg1);
-
-       value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
-       value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
-       writel(value, &regs->lcdc_lcdcfg2);
-
-       value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
-       value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
-       writel(value, &regs->lcdc_lcdcfg3);
-
-       /* Display size */
-       value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
-       value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
-       writel(value, &regs->lcdc_lcdcfg4);
-
-       writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
-              &regs->lcdc_basecfg0);
-
-       switch (NBITS(panel_info.vl_bpix)) {
-       case 16:
-               writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
-                      &regs->lcdc_basecfg1);
-               break;
-       case 32:
-               writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
-                      &regs->lcdc_basecfg1);
-               break;
-       default:
-               BUG();
-               break;
-       }
-
-       writel(LCDC_BASECFG2_XSTRIDE(0), &regs->lcdc_basecfg2);
-       writel(0, &regs->lcdc_basecfg3);
-       writel(LCDC_BASECFG4_DMA, &regs->lcdc_basecfg4);
-
-       /* Disable all interrupts */
-       writel(~0UL, &regs->lcdc_lcdidr);
-       writel(~0UL, &regs->lcdc_baseidr);
-
-       /* Setup the DMA descriptor, this descriptor will loop to itself */
-       desc = (struct lcd_dma_desc *)(lcdbase - 16);
-
-       desc->address = (u32)lcdbase;
-       /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
-       desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
-                       | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
-       desc->next = (u32)desc;
-
-       /* Flush the DMA descriptor if we enabled dcache */
-       flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
-
-       writel(desc->address, &regs->lcdc_baseaddr);
-       writel(desc->control, &regs->lcdc_basectrl);
-       writel(desc->next, &regs->lcdc_basenext);
-       writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
-              &regs->lcdc_basecher);
-
-       /* Enable LCD */
-       value = readl(&regs->lcdc_lcden);
-       writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
-       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
-                               true, 1000, false);
-       if (ret)
-               printf("%s: %d: Timeout!\n", __func__, __LINE__);
-       value = readl(&regs->lcdc_lcden);
-       writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
-       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
-                               true, 1000, false);
-       if (ret)
-               printf("%s: %d: Timeout!\n", __func__, __LINE__);
-       value = readl(&regs->lcdc_lcden);
-       writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
-       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
-                               true, 1000, false);
-       if (ret)
-               printf("%s: %d: Timeout!\n", __func__, __LINE__);
-       value = readl(&regs->lcdc_lcden);
-       writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
-       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
-                               true, 1000, false);
-       if (ret)
-               printf("%s: %d: Timeout!\n", __func__, __LINE__);
-
-       /* Enable flushing if we enabled dcache */
-       lcd_set_flush_dcache(1);
-}
-
-#else
-
 enum {
        LCD_MAX_WIDTH           = 1024,
        LCD_MAX_HEIGHT          = 768,
@@ -552,5 +341,3 @@ U_BOOT_DRIVER(atmel_hlcdfb) = {
        .of_to_plat = atmel_hlcdc_of_to_plat,
        .priv_auto      = sizeof(struct atmel_hlcdc_priv),
 };
-
-#endif

diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 7ac3c7cff4a1a745feed24a4f07c253c1f65b5e7..f0db193ede7433b2895f866d14ce15a7e1418ca3 100644 (file)
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -23,14 +23,12 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_DM_VIDEO
 enum {
        /* Maximum LCD size we support */
        LCD_MAX_WIDTH           = 1366,
        LCD_MAX_HEIGHT          = 768,
        LCD_MAX_LOG2_BPP        = VIDEO_BPP16,
 };
-#endif
 
 struct atmel_fb_priv {
        struct display_timing timing;
@@ -52,43 +50,6 @@ struct atmel_fb_priv {
 #define lcdc_readl(mmio, reg)          __raw_readl((mmio)+(reg))
 #define lcdc_writel(mmio, reg, val)    __raw_writel((val), (mmio)+(reg))
 
-#ifndef CONFIG_DM_VIDEO
-ushort *configuration_get_cmap(void)
-{
-       return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
-}
-
-#if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
-void fb_put_word(uchar **fb, uchar **from)
-{
-       *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
-       *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
-       *from += 2;
-}
-#endif
-
-void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
-{
-#if defined(CONFIG_ATMEL_LCD_BGR555)
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
-                   (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
-#else
-       lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
-                   (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
-#endif
-}
-
-void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
-{
-       int i;
-
-       for (i = 0; i < colors; ++i) {
-               struct bmp_color_table_entry cte = bmp->color_table[i];
-               lcd_setcolreg(i, cte.red, cte.green, cte.blue);
-       }
-}
-#endif
-
 static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
                          bool tft, bool cont_pol_low, ulong lcdbase)
 {
@@ -183,41 +144,6 @@ static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
                    (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
 }
 
-#ifndef CONFIG_DM_VIDEO
-void lcd_ctrl_init(void *lcdbase)
-{
-       struct display_timing timing;
-
-       timing.flags = 0;
-       if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
-               timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
-       if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
-               timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
-       timing.pixelclock.typ = panel_info.vl_clk;
-
-       timing.hactive.typ = panel_info.vl_col;
-       timing.hfront_porch.typ = panel_info.vl_right_margin;
-       timing.hback_porch.typ = panel_info.vl_left_margin;
-       timing.hsync_len.typ = panel_info.vl_hsync_len;
-
-       timing.vactive.typ = panel_info.vl_row;
-       timing.vfront_porch.typ = panel_info.vl_clk;
-       timing.vback_porch.typ = panel_info.vl_clk;
-       timing.vsync_len.typ = panel_info.vl_clk;
-
-       atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
-                     panel_info.vl_tft, panel_info.vl_cont_pol_low,
-                     (ulong)lcdbase);
-}
-
-ulong calc_fbsize(void)
-{
-       return ((panel_info.vl_col * panel_info.vl_row *
-               NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
-}
-#endif
-
-#ifdef CONFIG_DM_VIDEO
 static int atmel_fb_lcd_probe(struct udevice *dev)
 {
        struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
@@ -284,4 +210,3 @@ U_BOOT_DRIVER(atmel_fb) = {
        .plat_auto      = sizeof(struct atmel_lcd_plat),
        .priv_auto      = sizeof(struct atmel_fb_priv),
 };
-#endif