]> git.baikalelectronics.ru Git - kernel.git/commitdiff
soc: sifive: ccache: define the macro for the register shifts
authorZong Li <zong.li@sifive.com>
Tue, 13 Sep 2022 06:18:16 +0000 (06:18 +0000)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 13 Oct 2022 18:06:55 +0000 (11:06 -0700)
Define the macro for the register shifts, it could make the code be
more readable

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220913061817.22564-7-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
drivers/soc/sifive/sifive_ccache.c

index 91f0c2b32ea2bf4951005e670980ed0aafff07fd..1c171150e878d5bb0481c020d4fba2c73c92f879 100644 (file)
@@ -13,6 +13,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
 #include <linux/device.h>
+#include <linux/bitfield.h>
 #include <asm/cacheinfo.h>
 #include <soc/sifive/sifive_ccache.h>
 
 #define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
 
 #define SIFIVE_CCACHE_CONFIG 0x00
+#define SIFIVE_CCACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0)
+#define SIFIVE_CCACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8)
+#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)
+#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)
+
 #define SIFIVE_CCACHE_WAYENABLE 0x08
 #define SIFIVE_CCACHE_ECCINJECTERR 0x40
 
@@ -87,11 +93,11 @@ static void ccache_config_read(void)
        u32 cfg;
 
        cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
-
-       pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
-               (cfg & 0xff), (cfg >> 8) & 0xff,
-               BIT_ULL((cfg >> 16) & 0xff),
-               BIT_ULL((cfg >> 24) & 0xff));
+       pr_info("%llu banks, %llu ways, sets/bank=%llu, bytes/block=%llu\n",
+               FIELD_GET(SIFIVE_CCACHE_CONFIG_BANK_MASK, cfg),
+               FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, cfg),
+               BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_SETS_MASK, cfg)),
+               BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_BLKS_MASK, cfg)));
 
        cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
        pr_info("Index of the largest way enabled: %u\n", cfg);