drm/i915/tgl: Do modeset to enable and configure DC3CO exitline

DC3CO enabling B.Specs sequence requires to enable end configure
exit scanlines to TRANS_EXITLINE register, programming this register
has to be part of modeset sequence as this can't be change when
transcoder or port is enabled.
When system boots with only eDP panel there may not be real
modeset as BIOS has already programmed the necessary registers,
therefore it needs to force a modeset to enable and configure
DC3CO exitline.

v1: Computing dc3co_exitline crtc state from a DP encoder
    compute config. [Imre]
    Enabling and disabling DC3CO PSR2 transcoder exitline from
    encoder pre_enable and post_disable hooks. [Imre]
    Computing dc3co_exitline instead of has_dc3co_exitline bool. [Imre]
v2: Code refactoring for symmetry and to avoid exported function. [Imre]
    Removing IS_TIGERLAKE check from compute_config, adding PIPE_A
    restriction and clearing dc3co_exitline state if crtc is not active
    or it is not PSR2 capable in dc3co exitline compute_config. [Imre]
    Using GEN >= 12 check in dc3co exitline get_config. [Imre]

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191003081738.22101-5-anshuman.gupta@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3c1e885e01877f3d1b9edbcb3ec722a11ba5e49b..6c1315c7bcde1bfc3608d589690b93816253a40d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -45,6 +45,7 @@
 #include "intel_lspcon.h"
 #include "intel_panel.h"
 #include "intel_psr.h"
+#include "intel_sprite.h"
 #include "intel_tc.h"
 #include "intel_vdsc.h"
 
@@ -3330,6 +3331,86 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
        POSTING_READ(intel_dp->regs.dp_tp_ctl);
 }
 
+static void
+tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
+{
+       struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+       u32 val;
+
+       if (!cstate->dc3co_exitline)
+               return;
+
+       val = I915_READ(EXITLINE(cstate->cpu_transcoder));
+       val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
+       I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
+}
+
+static void
+tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
+{
+       u32 val, exit_scanlines;
+       struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+
+       if (!cstate->dc3co_exitline)
+               return;
+
+       exit_scanlines = cstate->dc3co_exitline;
+       exit_scanlines <<= EXITLINE_SHIFT;
+       val = I915_READ(EXITLINE(cstate->cpu_transcoder));
+       val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
+       val |= exit_scanlines;
+       val |= EXITLINE_ENABLE;
+       I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
+}
+
+static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
+                                             struct intel_crtc_state *cstate)
+{
+       u32 exit_scanlines;
+       struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+       u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
+
+       cstate->dc3co_exitline = 0;
+
+       if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
+               return;
+
+       /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
+       if (to_intel_crtc(cstate->base.crtc)->pipe != PIPE_A ||
+           encoder->port != PORT_A)
+               return;
+
+       if (!cstate->has_psr2 || !cstate->base.active)
+               return;
+
+       /*
+        * DC3CO Exit time 200us B.Spec 49196
+        * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
+        */
+       exit_scanlines =
+               intel_usecs_to_scanlines(&cstate->base.adjusted_mode, 200) + 1;
+
+       if (WARN_ON(exit_scanlines > crtc_vdisplay))
+               return;
+
+       cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines;
+       DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate->dc3co_exitline);
+}
+
+static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state)
+{
+       u32 val;
+       struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+
+       if (INTEL_GEN(dev_priv) < 12)
+               return;
+
+       val = I915_READ(EXITLINE(crtc_state->cpu_transcoder));
+
+       if (val & EXITLINE_ENABLE)
+               crtc_state->dc3co_exitline = val & EXITLINE_MASK;
+}
+
 static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
                                  const struct intel_crtc_state *crtc_state,
                                  const struct drm_connector_state *conn_state)
@@ -3342,6 +3423,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
        int level = intel_ddi_dp_level(intel_dp);
        enum transcoder transcoder = crtc_state->cpu_transcoder;
 
+       tgl_set_psr2_transcoder_exitline(crtc_state);
        intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
                                 crtc_state->lane_count, is_mst);
 
@@ -3666,6 +3748,7 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
                                                  dig_port->ddi_io_power_domain);
 
        intel_ddi_clk_disable(encoder);
+       tgl_clear_psr2_transcoder_exitline(old_crtc_state);
 }
 
 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
@@ -4212,6 +4295,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
                break;
        }
 
+       if (encoder->type == INTEL_OUTPUT_EDP)
+               tgl_dc3co_exitline_get_config(pipe_config);
+
        pipe_config->has_audio =
                intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
 
@@ -4289,10 +4375,13 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder,
        if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
                pipe_config->cpu_transcoder = TRANSCODER_EDP;
 
-       if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
+       if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
                ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
-       else
+       } else {
                ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
+               tgl_dc3co_exitline_compute_config(encoder, pipe_config);
+       }
+
        if (ret)
                return ret;
 

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 05fb672a00b92cafafd0170c9864fe08cdd753ed..1a533ccdb54f34db11e46f3a385b3bfce8491128 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12808,6 +12808,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
        PIPE_CONF_CHECK_I(pixel_multiplier);
        PIPE_CONF_CHECK_I(output_format);
+       PIPE_CONF_CHECK_I(dc3co_exitline);
        PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
        if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
            IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1602aac7ca0fe4b0b157423302f0210ba619fb0a..40390d85581523b0bd68ffdb74c0eb0523a3fe58 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -870,6 +870,7 @@ struct intel_crtc_state {
 
        bool has_psr;
        bool has_psr2;
+       u32 dc3co_exitline;
 
        /*
         * Frequence the dpll for the port should run at. Differs from the