]> git.baikalelectronics.ru Git - uboot.git/commitdiff
phy: marvell: cp110: Support SATA invert polarity
authorDenis Odintsov <shiva@mail.ru>
Wed, 15 Sep 2021 13:45:31 +0000 (15:45 +0200)
committerRamon Fried <rfried.dev@gmail.com>
Tue, 28 Sep 2021 15:50:55 +0000 (18:50 +0300)
In commit dfb551cb cp110 configuration initially done in u-boot
was removed and delegated to atf firmware as smc call.
That commit didn't account for later introduced in 898f527e SATA invert polarity support.

This patch adds support of passing SATA invert polarity flags to atf
firmware during the smc call.

Signed-off-by: Denis Odintsov <shiva@mail.ru>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
drivers/phy/marvell/comphy_cp110.c

index 418318d12f6bd342a91549efb96ee9fd60b1fa9d..4fe2dfcdd171116153f09ed8fae025684482b29a 100644 (file)
@@ -36,6 +36,10 @@ DECLARE_GLOBAL_DATA_PTR;
                        (COMPHY_CALLER_UBOOT | ((pcie_width) << 18) |   \
                        ((clk_src) << 17) | COMPHY_FW_FORMAT(mode, 0, speeds))
 
+/* Invert polarity are bits 1-0 of the mode */
+#define COMPHY_FW_SATA_FORMAT(mode, invert)    \
+                       ((invert) | COMPHY_FW_MODE_FORMAT(mode))
+
 #define COMPHY_SATA_MODE       0x1
 #define COMPHY_SGMII_MODE      0x2     /* SGMII 1G */
 #define COMPHY_HS_SGMII_MODE   0x3     /* SGMII 2.5G */
@@ -607,7 +611,8 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
                        break;
                case COMPHY_TYPE_SATA0:
                case COMPHY_TYPE_SATA1:
-                       mode =  COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE);
+                       mode = COMPHY_FW_SATA_FORMAT(COMPHY_SATA_MODE,
+                                                    serdes_map[lane].invert);
                        ret = comphy_sata_power_up(lane, hpipe_base_addr,
                                                   comphy_base_addr,
                                                   ptr_chip_cfg->cp_index,