drm/amdgpu: add RLC_PG_DELAY_3 for yellow carp

RLC_PG_DELAY_3 is to make RLC in safe mode to
prevent any misalignment or conflict in middle of any power
feature entry/exit sequence when CGPG feature is enabled.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index fbcdfcac1c2977f807fc48ee93d160ac52f1db4c..901267c4e44d409d67a56643d5804d0af5edbf3a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -8064,12 +8064,23 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
         * in refclk count. Note that RLC FW is modified to take 16 bits from
         * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
         *
-        * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us(0x4E20)
-        * as part of CGPG enablement starting point.
+        * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
+        * of CGPG enablement starting point.
+        * Power/performance team will optimize it and might give a new value later.
         */
-       if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) {
-               data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
-               WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
+       if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
+               switch (adev->asic_type) {
+               case CHIP_VANGOGH:
+                       data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
+                       WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
+                       break;
+               case CHIP_YELLOW_CARP:
+                       data = 0x1388 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
+                       WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
+                       break;
+               default:
+                       break;
+               }
        }
 }