drm/i915/perf: refactor perf setup

Gen8/9 aren't very different and we can merge some of this code.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171110190845.32574-4-lionel.g.landwerlin@intel.com

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 7271debe0417490c7205b6ee77035855c922da81..802928c54f066f37aa42c6f4c68ea2394dee4a9b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3423,41 +3423,46 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
                 * worth the complexity to maintain now that BDW+ enable
                 * execlist mode by default.
                 */
-               dev_priv->perf.oa.ops.is_valid_b_counter_reg =
-                       gen7_is_valid_b_counter_addr;
-               dev_priv->perf.oa.ops.is_valid_mux_reg =
-                       gen8_is_valid_mux_addr;
-               dev_priv->perf.oa.ops.is_valid_flex_reg =
-                       gen8_is_valid_flex_addr;
+               dev_priv->perf.oa.oa_formats = gen8_plus_oa_formats;
 
                dev_priv->perf.oa.ops.init_oa_buffer = gen8_init_oa_buffer;
-               dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set;
-               dev_priv->perf.oa.ops.disable_metric_set = gen8_disable_metric_set;
                dev_priv->perf.oa.ops.oa_enable = gen8_oa_enable;
                dev_priv->perf.oa.ops.oa_disable = gen8_oa_disable;
                dev_priv->perf.oa.ops.read = gen8_oa_read;
                dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
 
-               dev_priv->perf.oa.oa_formats = gen8_plus_oa_formats;
-
-               if (IS_GEN8(dev_priv)) {
-                       dev_priv->perf.oa.ctx_oactxctrl_offset = 0x120;
-                       dev_priv->perf.oa.ctx_flexeu0_offset = 0x2ce;
+               if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv)) {
+                       dev_priv->perf.oa.ops.is_valid_b_counter_reg =
+                               gen7_is_valid_b_counter_addr;
+                       dev_priv->perf.oa.ops.is_valid_mux_reg =
+                               gen8_is_valid_mux_addr;
+                       dev_priv->perf.oa.ops.is_valid_flex_reg =
+                               gen8_is_valid_flex_addr;
 
-                       dev_priv->perf.oa.timestamp_frequency = 12500000;
-
-                       dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<25);
                        if (IS_CHERRYVIEW(dev_priv)) {
                                dev_priv->perf.oa.ops.is_valid_mux_reg =
                                        chv_is_valid_mux_addr;
                        }
-               } else if (IS_GEN9(dev_priv)) {
-                       dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
-                       dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
 
-                       dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
+                       dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set;
+                       dev_priv->perf.oa.ops.disable_metric_set = gen8_disable_metric_set;
+
+                       if (IS_GEN8(dev_priv)) {
+                               dev_priv->perf.oa.ctx_oactxctrl_offset = 0x120;
+                               dev_priv->perf.oa.ctx_flexeu0_offset = 0x2ce;
+
+                               dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<25);
+                       } else {
+                               dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
+                               dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
+
+                               dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
+                       }
 
                        switch (dev_priv->info.platform) {
+                       case INTEL_BROADWELL:
+                               dev_priv->perf.oa.timestamp_frequency = 12500000;
+                               break;
                        case INTEL_BROXTON:
                        case INTEL_GEMINILAKE:
                                dev_priv->perf.oa.timestamp_frequency = 19200000;
@@ -3468,9 +3473,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
                                dev_priv->perf.oa.timestamp_frequency = 12000000;
                                break;
                        default:
-                               /* Leave timestamp_frequency to 0 so we can
-                                * detect unsupported platforms.
-                                */
                                break;
                        }
                }