ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK

Add default fitImage file bundling FPGA bitstreams for Arria10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

diff --git a/board/altera/arria10-socdk/fit_spl_fpga.its b/board/altera/arria10-socdk/fit_spl_fpga.its
new file mode 100644 (file)
index 0000000..adae997
--- /dev/null
+++ b/board/altera/arria10-socdk/fit_spl_fpga.its
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+ /*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+/dts-v1/;
+
+/ {
+       description = "FIT image with FPGA bistream";
+       #address-cells = <1>;
+
+       images {
+               fpga-periph-1 {
+                       description = "FPGA peripheral bitstream";
+                       data = /incbin/("../../../ghrd_10as066n2.periph.rbf");
+                       type = "fpga";
+                       arch = "arm";
+                       compression = "none";
+               };
+
+               fpga-core-1 {
+                       description = "FPGA core bitstream";
+                       data = /incbin/("../../../ghrd_10as066n2.core.rbf");
+                       type = "fpga";
+                       arch = "arm";
+                       compression = "none";
+               };
+       };
+
+       configurations {
+               default = "config-1";
+               config-1 {
+                       description = "Boot with FPGA early IO release config";
+                       fpga = "fpga-periph-1", "fpga-core-1";
+               };
+       };
+};