drm/i915/cnl: Also need power well sanitize.

The workaround added in
commit 6232c06d852a ("drm/i915/gen9: Reset secondary power well
equests left on by DMC/KVMR")
needs to be applied on Cannonlake as well.

So let's assume any platform using this power well setup
will also need and let's just go ahead and remove if condition.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1496781040-20888-11-git-send-email-rodrigo.vivi@intel.com

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 0b3cacd29baca2ebb42e21ed8a273848791dfdc1..8a6f287d225b181159919801cd93b8e18fded434 100644 (file)
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -853,8 +853,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
                        DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
                }
 
-               if (IS_GEN9(dev_priv))
-                       gen9_sanitize_power_well_requests(dev_priv, power_well);
+               gen9_sanitize_power_well_requests(dev_priv, power_well);
        }
 
        if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,