drm/i915/gvt: Fix incorrect mask of mmio 0x22028 in gen8/9 mmio list

According to GFX PRM on 01.org, bit 31:16 of mmio 0x22028 should be masks.

Fixes: 4ddec1753077 ("drm/i915/gvt: vGPU context switch")
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Colin Xu <colin.xu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 76630fbe51b6d70e26ccb2aa3866fdfe6d0620ac..e7e14c842be46d57bc583071a19d83b6b287790d 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -68,7 +68,7 @@ static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
        {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
        {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
        {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
-       {BCS0, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
+       {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
        {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
 };
 
@@ -119,7 +119,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
        {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
        {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
        {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
-       {BCS0, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
+       {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
 
        {VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */