media: s5p-mfc: Fix in register read and write for H264

[ Upstream commit 06710cd5d2436135046898d7e4b9408c8bb99446 ]

Few of the H264 encoder registers written were not getting reflected
since the read values were not stored and getting overwritten.

Fixes: 31cff37f2c42 ("[media] s5p-mfc: Add variants to access mfc registers")
Cc: stable@vger.kernel.org
Cc: linux-fsd@tesla.com
Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
index a1453053e31aba1ee1b57e16835e04648ee8a51c..ef8169f6c428c069a8acc89ef30c3696dff4d923 100644 (file)
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
@@ -1060,7 +1060,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
        }
 
        /* aspect ratio VUI */
-       readl(mfc_regs->e_h264_options);
+       reg = readl(mfc_regs->e_h264_options);
        reg &= ~(0x1 << 5);
        reg |= ((p_h264->vui_sar & 0x1) << 5);
        writel(reg, mfc_regs->e_h264_options);
@@ -1083,7 +1083,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
 
        /* intra picture period for H.264 open GOP */
        /* control */
-       readl(mfc_regs->e_h264_options);
+       reg = readl(mfc_regs->e_h264_options);
        reg &= ~(0x1 << 4);
        reg |= ((p_h264->open_gop & 0x1) << 4);
        writel(reg, mfc_regs->e_h264_options);
@@ -1097,23 +1097,23 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
        }
 
        /* 'WEIGHTED_BI_PREDICTION' for B is disable */
-       readl(mfc_regs->e_h264_options);
+       reg = readl(mfc_regs->e_h264_options);
        reg &= ~(0x3 << 9);
        writel(reg, mfc_regs->e_h264_options);
 
        /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */
-       readl(mfc_regs->e_h264_options);
+       reg = readl(mfc_regs->e_h264_options);
        reg &= ~(0x1 << 14);
        writel(reg, mfc_regs->e_h264_options);
 
        /* ASO */
-       readl(mfc_regs->e_h264_options);
+       reg = readl(mfc_regs->e_h264_options);
        reg &= ~(0x1 << 6);
        reg |= ((p_h264->aso & 0x1) << 6);
        writel(reg, mfc_regs->e_h264_options);
 
        /* hier qp enable */
-       readl(mfc_regs->e_h264_options);
+       reg = readl(mfc_regs->e_h264_options);
        reg &= ~(0x1 << 8);
        reg |= ((p_h264->open_gop & 0x1) << 8);
        writel(reg, mfc_regs->e_h264_options);
@@ -1134,7 +1134,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
        writel(reg, mfc_regs->e_h264_num_t_layer);
 
        /* frame packing SEI generation */
-       readl(mfc_regs->e_h264_options);
+       reg = readl(mfc_regs->e_h264_options);
        reg &= ~(0x1 << 25);
        reg |= ((p_h264->sei_frame_packing & 0x1) << 25);
        writel(reg, mfc_regs->e_h264_options);