drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap

GAM registers located in the 0x4xxx range have been relocated to 0xCxxx;
this is to make space for global MOCS registers.

v2: Rename register and bitfield to its new name (suggested by Mika)

HSD: 399379
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190823082055.5992-2-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
index edf194d23c6b15684f731367d8332b398ea9dbc5..1949346e714ee5f2ef304f7a92a05dd8aa79b5e0 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
@@ -83,6 +83,9 @@
 #define GEN8_GTCR                      _MMIO(0x4274)
 #define   GEN8_GTCR_INVALIDATE           (1<<0)
 
+#define GEN12_GUC_TLB_INV_CR           _MMIO(0xcee8)
+#define   GEN12_GUC_TLB_INV_CR_INVALIDATE      (1 << 0)
+
 #define GUC_ARAT_C6DIS                 _MMIO(0xA178)
 
 #define GUC_SHIM_CONTROL               _MMIO(0xc064)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0b81e0b643930dd44847bc113dec3f90f05897ac..2a425db1cfd89280654fb429dd4fbe0a82b8ead4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -132,9 +132,15 @@ static void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
 static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
        struct intel_uncore *uncore = ggtt->vm.gt->uncore;
+       struct drm_i915_private *i915 = ggtt->vm.i915;
 
        gen6_ggtt_invalidate(ggtt);
-       intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+       if (INTEL_GEN(i915) >= 12)
+               intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
+                                     GEN12_GUC_TLB_INV_CR_INVALIDATE);
+       else
+               intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 }
 
 static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)