drm/amdgpu: reroute vmc/utcl2 interrupts to ih ring 1 for arcturus

in case page faults overwhlem the interrupt handlers
and the driver lost the valuable interrupt information

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
index c8f92d261043332d2614fc0df5afa005af68dfe5..913b76396ba3eea6bd65655b6890aebb344a863a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
@@ -248,6 +248,38 @@ static int vega20_ih_enable_ring(struct amdgpu_device *adev,
        return 0;
 }
 
+/**
+ * vega20_ih_reroute_ih - reroute VMC/UTCL2 ih to an ih ring
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Reroute VMC and UMC interrupts on primary ih ring to
+ * ih ring 1 so they won't lose when bunches of page faults
+ * interrupts overwhelms the interrupt handler(VEGA20)
+ */
+static void vega20_ih_reroute_ih(struct amdgpu_device *adev)
+{
+       uint32_t tmp;
+
+       /* vega20 ih reroute will go through psp
+        * this function is only used for arcturus
+        */
+       if (adev->asic_type == CHIP_ARCTURUS) {
+               /* Reroute to IH ring 1 for VMC */
+               WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12);
+               tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
+               tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
+               tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+               WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
+
+               /* Reroute IH ring 1 for UTCL2 */
+               WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B);
+               tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
+               tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+               WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
+       }
+}
+
 /**
  * vega20_ih_irq_init - init and enable the interrupt ring
  *
@@ -289,6 +321,8 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev)
 
        for (i = 0; i < ARRAY_SIZE(ih); i++) {
                if (ih[i]->ring_size) {
+                       if (i == 1)
+                               vega20_ih_reroute_ih(adev);
                        ret = vega20_ih_enable_ring(adev, ih[i]);
                        if (ret)
                                return ret;