drm/i915/dg2: Define MOCS table for DG2

Bspec: 45101, 45427
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210904003544.2422282-3-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 8c3fbf4f323b9c79f330e7470bd93d86a180a61b..e4b97cd14cf97705d560f23969b7f42be83684d9 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -370,6 +370,30 @@ static const struct drm_i915_mocs_entry xehpsdv_mocs_table[] = {
        MOCS_ENTRY(63, 0, L3_1_UC),
 };
 
+static const struct drm_i915_mocs_entry dg2_mocs_table[] = {
+       /* UC - Coherent; GO:L3 */
+       MOCS_ENTRY(0, 0, L3_1_UC | L3_LKUP(1)),
+       /* UC - Coherent; GO:Memory */
+       MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
+       /* UC - Non-Coherent; GO:Memory */
+       MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),
+
+       /* WB - LC */
+       MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
+};
+
+static const struct drm_i915_mocs_entry dg2_mocs_table_g10_ax[] = {
+       /* Wa_14011441408: Set Go to Memory for MOCS#0 */
+       MOCS_ENTRY(0, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
+       /* UC - Coherent; GO:Memory */
+       MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
+       /* UC - Non-Coherent; GO:Memory */
+       MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),
+
+       /* WB - LC */
+       MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
+};
+
 enum {
        HAS_GLOBAL_MOCS = BIT(0),
        HAS_ENGINE_MOCS = BIT(1),
@@ -399,7 +423,18 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
        memset(table, 0, sizeof(struct drm_i915_mocs_table));
 
        table->unused_entries_index = I915_MOCS_PTE;
-       if (IS_XEHPSDV(i915)) {
+       if (IS_DG2(i915)) {
+               if (IS_DG2_GT_STEP(i915, G10, STEP_A0, STEP_B0)) {
+                       table->size = ARRAY_SIZE(dg2_mocs_table_g10_ax);
+                       table->table = dg2_mocs_table_g10_ax;
+               } else {
+                       table->size = ARRAY_SIZE(dg2_mocs_table);
+                       table->table = dg2_mocs_table;
+               }
+               table->uc_index = 1;
+               table->n_entries = GEN9_NUM_MOCS_ENTRIES;
+               table->unused_entries_index = 3;
+       } else if (IS_XEHPSDV(i915)) {
                table->size = ARRAY_SIZE(xehpsdv_mocs_table);
                table->table = xehpsdv_mocs_table;
                table->uc_index = 2;