]> git.baikalelectronics.ru Git - kernel.git/commitdiff
ice: Call ice_aq_set_mac_cfg
authorAnirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Sat, 16 May 2020 00:36:30 +0000 (17:36 -0700)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Sat, 23 May 2020 05:05:25 +0000 (22:05 -0700)
As per the specification, the driver needs to call set_mac_cfg
(opcode 0x0603) to be able to exercise jumbo frames. Call the
function during initialization and the post reset rebuild flow.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
drivers/net/ethernet/intel/ice/ice_common.c
drivers/net/ethernet/intel/ice/ice_common.h
drivers/net/ethernet/intel/ice/ice_hw_autogen.h
drivers/net/ethernet/intel/ice/ice_main.c

index deada2e3d7c075bcfc3cf5381a1c2e61521ff778..f80fb6570f8f8c83265c50b508266cc3d3d75483 100644 (file)
@@ -1068,6 +1068,25 @@ struct ice_aqc_set_phy_cfg_data {
        u8 rsvd1;
 };
 
+/* Set MAC Config command data structure (direct 0x0603) */
+struct ice_aqc_set_mac_cfg {
+       __le16 max_frame_size;
+       u8 params;
+#define ICE_AQ_SET_MAC_PACE_S          3
+#define ICE_AQ_SET_MAC_PACE_M          (0xF << ICE_AQ_SET_MAC_PACE_S)
+#define ICE_AQ_SET_MAC_PACE_TYPE_M     BIT(7)
+#define ICE_AQ_SET_MAC_PACE_TYPE_RATE  0
+#define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
+       u8 tx_tmr_priority;
+       __le16 tx_tmr_value;
+       __le16 fc_refresh_threshold;
+       u8 drop_opts;
+#define ICE_AQ_SET_MAC_AUTO_DROP_MASK          BIT(0)
+#define ICE_AQ_SET_MAC_AUTO_DROP_NONE          0
+#define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
+       u8 reserved[7];
+};
+
 /* Restart AN command data structure (direct 0x0605)
  * Also used for response, with only the lport_num field present.
  */
@@ -1774,6 +1793,7 @@ struct ice_aq_desc {
                struct ice_aqc_download_pkg download_pkg;
                struct ice_aqc_set_mac_lb set_mac_lb;
                struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
+               struct ice_aqc_set_mac_cfg set_mac_cfg;
                struct ice_aqc_set_event_mask set_event_mask;
                struct ice_aqc_get_link_status get_link_status;
                struct ice_aqc_event_lan_overflow lan_overflow;
@@ -1870,6 +1890,7 @@ enum ice_adminq_opc {
        /* PHY commands */
        ice_aqc_opc_get_phy_caps                        = 0x0600,
        ice_aqc_opc_set_phy_cfg                         = 0x0601,
+       ice_aqc_opc_set_mac_cfg                         = 0x0603,
        ice_aqc_opc_restart_an                          = 0x0605,
        ice_aqc_opc_get_link_status                     = 0x0607,
        ice_aqc_opc_set_event_mask                      = 0x0613,
index 3a4c1415010709b93aebc3896e912122045b7ff6..0a0b00fffaf7761402800f55454d70684293d1a4 100644 (file)
@@ -315,6 +315,71 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
        return 0;
 }
 
+/**
+ * ice_fill_tx_timer_and_fc_thresh
+ * @hw: pointer to the HW struct
+ * @cmd: pointer to MAC cfg structure
+ *
+ * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
+ * descriptor
+ */
+static void
+ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
+                               struct ice_aqc_set_mac_cfg *cmd)
+{
+       u16 fc_thres_val, tx_timer_val;
+       u32 val;
+
+       /* We read back the transmit timer and FC threshold value of
+        * LFC. Thus, we will use index =
+        * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
+        *
+        * Also, because we are operating on transmit timer and FC
+        * threshold of LFC, we don't turn on any bit in tx_tmr_priority
+        */
+#define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
+
+       /* Retrieve the transmit timer */
+       val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
+       tx_timer_val = val &
+               PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
+       cmd->tx_tmr_value = cpu_to_le16(tx_timer_val);
+
+       /* Retrieve the FC threshold */
+       val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
+       fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
+
+       cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val);
+}
+
+/**
+ * ice_aq_set_mac_cfg
+ * @hw: pointer to the HW struct
+ * @max_frame_size: Maximum Frame Size to be supported
+ * @cd: pointer to command details structure or NULL
+ *
+ * Set MAC configuration (0x0603)
+ */
+enum ice_status
+ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
+{
+       struct ice_aqc_set_mac_cfg *cmd;
+       struct ice_aq_desc desc;
+
+       cmd = &desc.params.set_mac_cfg;
+
+       if (max_frame_size == 0)
+               return ICE_ERR_PARAM;
+
+       ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
+
+       cmd->max_frame_size = cpu_to_le16(max_frame_size);
+
+       ice_fill_tx_timer_and_fc_thresh(hw, cmd);
+
+       return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
+}
+
 /**
  * ice_init_fltr_mgmt_struct - initializes filter management list and locks
  * @hw: pointer to the HW struct
@@ -745,6 +810,10 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
        status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
        devm_kfree(ice_hw_to_dev(hw), mac_buf);
 
+       if (status)
+               goto err_unroll_fltr_mgmt_struct;
+       /* enable jumbo frame support at MAC level */
+       status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
        if (status)
                goto err_unroll_fltr_mgmt_struct;
        /* Obtain counter base index which would be used by flow director */
index 8104f3d64d964d6fc17e8c9f67ec2d7ff1544223..bea755a658eb70d4a89c124930f4abbd4e4f6824 100644 (file)
@@ -108,6 +108,8 @@ enum ice_status
 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
                           struct ice_sq_cd *cd);
 enum ice_status
+ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);
+enum ice_status
 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
                     struct ice_link_status *link, struct ice_sq_cd *cd);
 enum ice_status
index c8b037d25053e7d474b0986e85f84cc2060c887e..1f9b427a35fa9a5535d5f122c2157ab88e1b6edf 100644 (file)
 #define VPLAN_TX_QBASE_VFNUMQ_M                        ICE_M(0xFF, 16)
 #define VPLAN_TXQ_MAPENA(_VF)                  (0x00073800 + ((_VF) * 4))
 #define VPLAN_TXQ_MAPENA_TX_ENA_M              BIT(0)
+#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i)    (0x001E36E0 + ((_i) * 32))
+#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8
+#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M ICE_M(0xFFFF, 0)
+#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32))
+#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M ICE_M(0xFFFF, 0)
 #define GL_MDCK_TX_TDPU                                0x00049348
 #define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
 #define GL_MDET_RX                             0x00294C00
index c69567210584ac14ee23ab91d32da11406c4594a..220f1bfc63769cee00dc839f158bc533157c4615 100644 (file)
@@ -4901,6 +4901,12 @@ static void ice_rebuild(struct ice_pf *pf, enum ice_reset_req reset_type)
                goto err_init_ctrlq;
        }
 
+       ret = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
+       if (ret) {
+               dev_err(dev, "set_mac_cfg failed %s\n", ice_stat_str(ret));
+               goto err_init_ctrlq;
+       }
+
        err = ice_sched_init_port(hw->port_info);
        if (err)
                goto err_sched_init_port;