CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0x100
+CONFIG_SYS_NAND_MAX_ECCPOS=1664
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
CONFIG_CONS_INDEX=2
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_MAX_ECCPOS=1664
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_AXP_ELDO2_VOLT=1800
CONFIG_CONS_INDEX=5
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=56
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_DRIVER_TI_EMAC_USE_RMII=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_EON=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_EON=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_EON=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_EON=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FSL_IFC=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=56
CONFIG_SMC911X=y
CONFIG_SMC911X_32_BIT=y
CONFIG_PINCTRL=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=56
CONFIG_SMC911X=y
CONFIG_SMC911X_32_BIT=y
CONFIG_PINCTRL=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=56
CONFIG_SMC911X=y
CONFIG_SMC911X_32_BIT=y
CONFIG_PINCTRL=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=56
CONFIG_SMC911X=y
CONFIG_SMC911X_32_BIT=y
CONFIG_PINCTRL=y
CONFIG_CMD_NAND_TORTURE
Enables the torture command (see description of this command below).
- CONFIG_SYS_NAND_MAX_ECCPOS
- If specified, overrides the maximum number of ECC bytes
- supported. Useful for reducing image size, especially with SPL.
- This must be at least 48 if nand_base.c is used.
-
- CONFIG_SYS_NAND_MAX_OOBFREE
- If specified, overrides the maximum number of free OOB regions
- supported. Useful for reducing image size, especially with SPL.
- This must be at least 2 if nand_base.c is used.
-
CONFIG_SYS_NAND_MAX_CHIPS
The maximum number of NAND chips per device to be supported.
source "drivers/mtd/nand/Kconfig"
+config SYS_NAND_MAX_OOBFREE
+ int "Maximum number of free OOB regions supported"
+ depends on SAMSUNG_ONENAND || MTD_RAW_NAND
+ range 2 32
+ default 32
+ help
+ Set the maximum number of free OOB regions supported. Useful for
+ reducing image size, especially with SPL.
+
+config SYS_NAND_MAX_ECCPOS
+ int "Maximum number of ECC bytes supported"
+ depends on SAMSUNG_ONENAND || MTD_RAW_NAND
+ range 48 2147483647
+ default 680
+ help
+ Set the maximum number of ECC bytes supported. Useful for reducing
+ image size, especially with SPL.
+
config SYS_NAND_MAX_CHIPS
int "NAND max chips"
depends on MTD_RAW_NAND || CMD_ONENAND || TARGET_S5PC210_UNIVERSAL || \
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 13
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-#define CONFIG_SYS_NAND_MAX_ECCPOS 56
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
/* NAND block size is 128 KiB. Synchronize these values with
* corresponding Device Tree entries in Linux:
#endif
#endif
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
#endif
#endif
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 13
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-#define CONFIG_SYS_NAND_MAX_ECCPOS 56
#endif
/* Environment information */
#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
-#ifdef CONFIG_NAND_SUNXI
-#define CONFIG_SYS_NAND_MAX_ECCPOS 1664
-#endif
-
/* mmc config */
#define CONFIG_MMC_SUNXI_SLOT 0