drm/i915/guc: Apply Wa_16011777198

Enable GuC Wa to reset RCS/CCS before it goes into RC6.

Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220415224025.3693037-5-umesh.nerlige.ramappa@intel.com

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index fd04c4cd9d44db7639d4fbc7f75e3de929db056f..830889349756a02fe0a5fdf1356d3912971fafa4 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -310,6 +310,11 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
        if (GRAPHICS_VER(gt->i915) == 12)
                flags |= GUC_WA_PRE_PARSER;
 
+       /* Wa_16011777198:dg2 */
+       if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
+           IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
+               flags |= GUC_WA_RCS_RESET_BEFORE_RC6;
+
        return flags;
 }
 

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index fe5751f67b1946cd68d81808c26eb85e5b066e4c..126e67ea1619b1432af427b50315eda38fec630e 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -100,6 +100,7 @@
 #define GUC_CTL_WA                     1
 #define   GUC_WA_GAM_CREDITS           BIT(10)
 #define   GUC_WA_DUAL_QUEUE            BIT(11)
+#define   GUC_WA_RCS_RESET_BEFORE_RC6  BIT(13)
 #define   GUC_WA_PRE_PARSER            BIT(14)
 #define   GUC_WA_POLLCS                        BIT(18)