The alignment should match the page size for secure buffer, so we didn't
configure it anymore.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
resv = vm->root.base.bo->tbo.base.resv;
}
- if (flags & AMDGPU_GEM_CREATE_ENCRYPTED) {
- /* XXX: pad out alignment to meet TMZ requirements */
- }
-
r = amdgpu_gem_object_create(adev, size, args->in.alignment,
(u32)(0xffffffff & args->in.domains),
flags, ttm_bo_type_device, resv, &gobj);