]> git.baikalelectronics.ru Git - kernel.git/commitdiff
powerpc/xive: Use XIVE_BAD_IRQ instead of zero to catch non configured IPIs
authorCédric Le Goater <clg@kaod.org>
Fri, 6 Mar 2020 15:01:40 +0000 (16:01 +0100)
committerMichael Ellerman <mpe@ellerman.id.au>
Thu, 26 Mar 2020 13:19:04 +0000 (00:19 +1100)
When a CPU is brought up, an IPI number is allocated and recorded
under the XIVE CPU structure. Invalid IPI numbers are tracked with
interrupt number 0x0.

On the PowerNV platform, the interrupt number space starts at 0x10 and
this works fine. However, on the sPAPR platform, it is possible to
allocate the interrupt number 0x0 and this raises an issue when CPU 0
is unplugged. The XIVE spapr driver tracks allocated interrupt numbers
in a bitmask and it is not correctly updated when interrupt number 0x0
is freed. It stays allocated and it is then impossible to reallocate.

Fix by using the XIVE_BAD_IRQ value instead of zero on both platforms.

Reported-by: David Gibson <david@gibson.dropbear.id.au>
Fixes: eac1e731b59e ("powerpc/xive: guest exploitation of the XIVE interrupt controller")
Cc: stable@vger.kernel.org # v4.14+
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Tested-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200306150143.5551-2-clg@kaod.org
arch/powerpc/sysdev/xive/common.c
arch/powerpc/sysdev/xive/native.c
arch/powerpc/sysdev/xive/spapr.c
arch/powerpc/sysdev/xive/xive-internal.h

index 9651ca061828a06be50d5636508d90505fdcfcc2..0e918fe6a4ecfbcdebd28d282ea42c1378d817d2 100644 (file)
@@ -68,13 +68,6 @@ static u32 xive_ipi_irq;
 /* Xive state for each CPU */
 static DEFINE_PER_CPU(struct xive_cpu *, xive_cpu);
 
-/*
- * A "disabled" interrupt should never fire, to catch problems
- * we set its logical number to this
- */
-#define XIVE_BAD_IRQ           0x7fffffff
-#define XIVE_MAX_IRQ           (XIVE_BAD_IRQ - 1)
-
 /* An invalid CPU target */
 #define XIVE_INVALID_TARGET    (-1)
 
@@ -1150,7 +1143,7 @@ static int xive_setup_cpu_ipi(unsigned int cpu)
        xc = per_cpu(xive_cpu, cpu);
 
        /* Check if we are already setup */
-       if (xc->hw_ipi != 0)
+       if (xc->hw_ipi != XIVE_BAD_IRQ)
                return 0;
 
        /* Grab an IPI from the backend, this will populate xc->hw_ipi */
@@ -1187,7 +1180,7 @@ static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc)
        /* Disable the IPI and free the IRQ data */
 
        /* Already cleaned up ? */
-       if (xc->hw_ipi == 0)
+       if (xc->hw_ipi == XIVE_BAD_IRQ)
                return;
 
        /* Mask the IPI */
@@ -1343,6 +1336,7 @@ static int xive_prepare_cpu(unsigned int cpu)
                if (np)
                        xc->chip_id = of_get_ibm_chip_id(np);
                of_node_put(np);
+               xc->hw_ipi = XIVE_BAD_IRQ;
 
                per_cpu(xive_cpu, cpu) = xc;
        }
index 0ff6b739052c8fc63daaba039d0a0889d14906de..50e1a8e02497dded6c85dcfae185bef1cbd7d680 100644 (file)
@@ -312,7 +312,7 @@ static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc)
        s64 rc;
 
        /* Free the IPI */
-       if (!xc->hw_ipi)
+       if (xc->hw_ipi == XIVE_BAD_IRQ)
                return;
        for (;;) {
                rc = opal_xive_free_irq(xc->hw_ipi);
@@ -320,7 +320,7 @@ static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc)
                        msleep(OPAL_BUSY_DELAY_MS);
                        continue;
                }
-               xc->hw_ipi = 0;
+               xc->hw_ipi = XIVE_BAD_IRQ;
                break;
        }
 }
index 55dc61cb4867b1afd6cbaf1eb2c81d8d0eb295a2..3f15615712b5b411080c77276d966d7e4d484e1d 100644 (file)
@@ -560,11 +560,11 @@ static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc)
 
 static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc)
 {
-       if (!xc->hw_ipi)
+       if (xc->hw_ipi == XIVE_BAD_IRQ)
                return;
 
        xive_irq_bitmap_free(xc->hw_ipi);
-       xc->hw_ipi = 0;
+       xc->hw_ipi = XIVE_BAD_IRQ;
 }
 #endif /* CONFIG_SMP */
 
index 59cd366e7933a7233cc63a32daf3a04a5426ad4d..382980f4de2d227bc4a572102d1fed1c98d95cb7 100644 (file)
@@ -5,6 +5,13 @@
 #ifndef __XIVE_INTERNAL_H
 #define __XIVE_INTERNAL_H
 
+/*
+ * A "disabled" interrupt should never fire, to catch problems
+ * we set its logical number to this
+ */
+#define XIVE_BAD_IRQ           0x7fffffff
+#define XIVE_MAX_IRQ           (XIVE_BAD_IRQ - 1)
+
 /* Each CPU carry one of these with various per-CPU state */
 struct xive_cpu {
 #ifdef CONFIG_SMP