]> git.baikalelectronics.ru Git - kernel.git/commitdiff
drm/amdgpu: put SMU into proper state on runpm suspending for BOCO capable platform
authorEvan Quan <evan.quan@amd.com>
Fri, 17 Dec 2021 11:05:06 +0000 (19:05 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 27 Dec 2021 18:08:28 +0000 (13:08 -0500)
By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some proper cleanups and
put itself into a state ready for PNP. That can workaround some random resuming
failure observed on BOCO capable platforms.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

index 1a97b8b237d5d56a58b458f0c00d152fa2c73011..86ca80da9eea8299b35cda84cbdf548418df6408 100644 (file)
@@ -2238,12 +2238,27 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
        if (amdgpu_device_supports_px(drm_dev))
                drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 
+       /*
+        * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
+        * proper cleanups and put itself into a state ready for PNP. That
+        * can address some random resuming failure observed on BOCO capable
+        * platforms.
+        * TODO: this may be also needed for PX capable platform.
+        */
+       if (amdgpu_device_supports_boco(drm_dev))
+               adev->mp1_state = PP_MP1_STATE_UNLOAD;
+
        ret = amdgpu_device_suspend(drm_dev, false);
        if (ret) {
                adev->in_runpm = false;
+               if (amdgpu_device_supports_boco(drm_dev))
+                       adev->mp1_state = PP_MP1_STATE_NONE;
                return ret;
        }
 
+       if (amdgpu_device_supports_boco(drm_dev))
+               adev->mp1_state = PP_MP1_STATE_NONE;
+
        if (amdgpu_device_supports_px(drm_dev)) {
                /* Only need to handle PCI state in the driver for ATPX
                 * PCI core handles it for _PR3.