u32 time_out;
u32 value;
uint clk;
+ u32 hostver;
if (clock < mmc->cfg->f_min)
clock = mmc->cfg->f_min;
esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
+ /* Only newer eSDHC controllers set PRSSTAT_SDSTB flag */
+ hostver = esdhc_read32(&priv->esdhc_regs->hostver);
+ if (HOSTVER_VENDOR(hostver) <= VENDOR_V_22) {
+ udelay(10000);
+ esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
+ return;
+ }
+
time_out = 20;
value = PRSSTAT_SDSTB;
while (!(esdhc_read32(®s->prsstat) & value)) {
struct fsl_esdhc *regs = priv->esdhc_regs;
u32 value;
u32 time_out;
+ u32 hostver;
value = esdhc_read32(®s->sysctl);
esdhc_write32(®s->sysctl, value);
+ /* Only newer eSDHC controllers set PRSSTAT_SDSTB flag */
+ hostver = esdhc_read32(&priv->esdhc_regs->hostver);
+ if (HOSTVER_VENDOR(hostver) <= VENDOR_V_22) {
+ udelay(10000);
+ return;
+ }
+
time_out = 20;
value = PRSSTAT_SDSTB;
while (!(esdhc_read32(®s->prsstat) & value)) {