plat: tc0: Enable SPMC execution at S-EL2

This patch enables SPMC execution at S-EL2 by adding below changes

    - Map TC0_MAP_TZC_DRAM1 for loading SPMC
    - Add details of cactus test secure partitions
    - Adds tc0 spmc manifest file with details on secure partitions
    - Inlcude TOS_FW_CONFIG when SPM is spmd
    - Increases bl2 image size

SPMC at S-EL2 is only enabled when build with SPD=spmd.

Change-Id: I4c5f70911903c232ee8ecca57f1e288d6b1cd647
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

diff --git a/plat/arm/board/tc0/fdts/tc0_fw_config.dts b/plat/arm/board/tc0/fdts/tc0_fw_config.dts
index 381ce1fcb813f54bf183e400e208547422b3cdfd..4b6abd4d19bbeeae11622848b24d45d56d649d7e 100644 (file)
--- a/plat/arm/board/tc0/fdts/tc0_fw_config.dts
+++ b/plat/arm/board/tc0/fdts/tc0_fw_config.dts
@@ -14,10 +14,16 @@
 
                tb_fw-config {
                        load-address = <0x0 0x4001300>;
-                       max-size = <0x200>;
+                       max-size = <0x400>;
                        id = <TB_FW_CONFIG_ID>;
                };
 
+               tos_fw-config {
+                       load-address = <0x0 0x04001700>;
+                       max-size = <0x1000>;
+                       id = <TOS_FW_CONFIG_ID>;
+               };
+
                hw-config {
                        load-address = <0x0 0x83000000>;
                        max-size = <0x01000000>;

diff --git a/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts b/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts
new file mode 100644 (file)
index 0000000..b6c543a
--- /dev/null
+++ b/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/dts-v1/;
+
+/ {
+       compatible = "arm,ffa-core-manifest-1.0";
+       #address-cells = <2>;
+       #size-cells = <1>;
+
+       attribute {
+               spmc_id = <0x8000>;
+               maj_ver = <0x1>;
+               min_ver = <0x0>;
+               exec_state = <0x0>;
+               load_address = <0x0 0xfd000000>;
+               entrypoint = <0x0 0xfd000000>;
+               binary_size = <0x80000>;
+       };
+
+       chosen {
+               linux,initrd-start = <0>;
+               linux,initrd-end = <0>;
+       };
+
+       hypervisor {
+               compatible = "hafnium,hafnium";
+               vm1 {
+                       is_ffa_partition;
+                       debug_name = "cactus-primary";
+                       load_address = <0xfe000000>;
+               };
+               vm2 {
+                       is_ffa_partition;
+                       debug_name = "cactus-secondary";
+                       load_address = <0xfe100000>;
+                       vcpu_count = <4>;
+                       mem_size = <1048576>;
+               };
+               vm3 {
+                       is_ffa_partition;
+                       debug_name = "cactus-tertiary";
+                       load_address = <0xfe200000>;
+                       vcpu_count = <4>;
+                       mem_size = <1048576>;
+               };
+       };
+
+       cpus {
+               #address-cells = <0x2>;
+               #size-cells = <0x0>;
+
+               CPU0:cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,armv8";
+                       reg = <0x0 0x0>;
+                       enable-method = "psci";
+               };
+
+               /*
+                * SPM(Hafnium) requires secondary cpu nodes are declared in
+                * descending order
+                */
+               CPU3:cpu@300 {
+                       device_type = "cpu";
+                       compatible = "arm,armv8";
+                       reg = <0x0 0x300>;
+                       enable-method = "psci";
+               };
+
+               CPU2:cpu@200 {
+                       device_type = "cpu";
+                       compatible = "arm,armv8";
+                       reg = <0x0 0x200>;
+                       enable-method = "psci";
+               };
+
+               CPU1:cpu@100 {
+                       device_type = "cpu";
+                       compatible = "arm,armv8";
+                       reg = <0x0 0x100>;
+                       enable-method = "psci";
+               };
+       };
+
+       /* 32MB of TC0_TZC_DRAM1_BASE */
+       memory@fd000000 {
+               device_type = "memory";
+               reg = <0x0 0xfd000000 0x2000000>;
+       };
+};

diff --git a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
index 2fd25d9b4262ed77008b2dfc244ed1f079824404..3df94bf92b7d6e1219c011bb5068413e8bd655f8 100644 (file)
--- a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
+++ b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
@@ -24,4 +24,24 @@
                mbedtls_heap_addr = <0x0 0x0>;
                mbedtls_heap_size = <0x0>;
        };
+
+       secure-partitions {
+               compatible = "arm,sp";
+               cactus-primary {
+                       uuid = <0xb4b5671e 0x4a904fe1 0xb81ffb13 0xdae1dacb>;
+                       load-address = <0xfe000000>;
+                       owner = "SiP";
+               };
+
+               cactus-secondary {
+                       uuid = <0xd1582309 0xf02347b9 0x827c4464 0xf5578fc8>;
+                       load-address = <0xfe100000>;
+                       owner = "Plat";
+               };
+
+               cactus-tertiary {
+                       uuid = <0x79b55c73 0x1d8c44b9 0x859361e1 0x770ad8d2>;
+                       load-address = <0xfe200000>;
+               };
+       };
 };

diff --git a/plat/arm/board/tc0/include/platform_def.h b/plat/arm/board/tc0/include/platform_def.h
index 81b3944e5827eb6b1ba591c140c1f2298791bc53..dbec706faca7219808bd851dccc779c6578ea020 100644 (file)
--- a/plat/arm/board/tc0/include/platform_def.h
+++ b/plat/arm/board/tc0/include/platform_def.h
@@ -55,6 +55,14 @@
                                                TC0_TZC_DRAM1_BASE,     \
                                                TC0_TZC_DRAM1_SIZE,     \
                                                MT_MEMORY | MT_RW | MT_SECURE)
+/*
+ * Max size of SPMC is 2MB for tc0. With SPMD enabled this value corresponds to
+ * max size of BL32 image.
+ */
+#if defined(SPD_spmd)
+#define PLAT_ARM_SPMC_BASE             TC0_TZC_DRAM1_BASE
+#define PLAT_ARM_SPMC_SIZE             UL(0x200000)  /* 2 MB */
+#endif
 
 /*
  * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
@@ -106,7 +114,7 @@
 #if TRUSTED_BOARD_BOOT
 # define PLAT_ARM_MAX_BL2_SIZE         0x1E000
 #else
-# define PLAT_ARM_MAX_BL2_SIZE         0x11000
+# define PLAT_ARM_MAX_BL2_SIZE         0x14000
 #endif
 
 /*
@@ -241,4 +249,7 @@
 #define PLAT_ARM_TZC_NS_DEV_ACCESS     \
                (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT))
 
+/* virtual address used by dynamic mem_protect for chunk_base */
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME   UL(0xc0000000)
+
 #endif /* PLATFORM_DEF_H */

diff --git a/plat/arm/board/tc0/platform.mk b/plat/arm/board/tc0/platform.mk
index 4db081e708d8253fd861883296de2d9ccae07b4c..5d2cc38c463cfb58df1f9d1c773b8811157b8ce2 100644 (file)
--- a/plat/arm/board/tc0/platform.mk
+++ b/plat/arm/board/tc0/platform.mk
@@ -85,6 +85,14 @@ $(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
 # Add the TB_FW_CONFIG to FIP and specify the same to certtool
 $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
 
+ifeq (${SPD},spmd)
+FDT_SOURCES            +=      ${TC0_BASE}/fdts/${PLAT}_spmc_manifest.dts
+TC0_TOS_FW_CONFIG      :=      ${BUILD_PLAT}/fdts/${PLAT}_spmc_manifest.dtb
+
+# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${TC0_TOS_FW_CONFIG},--tos-fw-config,${TC0_TOS_FW_CONFIG}))
+endif
+
 #Device tree
 TC0_HW_CONFIG_DTS      :=      fdts/tc0.dts
 TC0_HW_CONFIG          :=      ${BUILD_PLAT}/fdts/${PLAT}.dtb

diff --git a/plat/arm/board/tc0/tc0_plat.c b/plat/arm/board/tc0/tc0_plat.c
index 304666a0169fa40f3ea72759e8ddc18265dd8466..e12ad56d81e95386c0ee81a9c96f8d6bd6dcd3b4 100644 (file)
--- a/plat/arm/board/tc0/tc0_plat.c
+++ b/plat/arm/board/tc0/tc0_plat.c
@@ -39,6 +39,9 @@ const mmap_region_t plat_arm_mmap[] = {
        TC0_FLASH0_RO,
        TC0_MAP_DEVICE,
        TC0_MAP_NS_DRAM1,
+#if defined(SPD_spmd)
+       TC0_MAP_TZC_DRAM1,
+#endif
 #if ARM_BL31_IN_DRAM
        ARM_MAP_BL31_SEC_DRAM,
 #endif