drm/i915: Add dedicated plane hook for async flip case

This hook is added to avoid writing other plane registers in case of
async flips, so that we do not write the double buffered registers
during async surface address update.

v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
    -Add a vfunc for skl_program_async_surface_address
     and call it from intel_update_plane. (Ville)

v8: -Rebased.

v9: -Use if-else instead of return in intel_update_plane(). (Ville)
    -Rename 'program_async_surface_address' to 'async_flip'. (Ville)

v10: -Check if async_flip hook is present before calling it.
      Otherwise it will OOPS during legacy cursor updates. (Ville)

v11: -Rename skl_program_async_surface_address(). (Ville)

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200921110210.21182-6-karthik.b.s@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 79032701873a2655be539deeb2d43ec4a57a41ba..6bd8e6cdd477120f0fc4b3cd8ac8b6c9904f8279 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -408,7 +408,11 @@ void intel_update_plane(struct intel_plane *plane,
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
        trace_intel_update_plane(&plane->base, crtc);
-       plane->update_plane(plane, crtc_state, plane_state);
+
+       if (crtc_state->uapi.async_flip && plane->async_flip)
+               plane->async_flip(plane, crtc_state, plane_state);
+       else
+               plane->update_plane(plane, crtc_state, plane_state);
 }
 
 void intel_disable_plane(struct intel_plane *plane,

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 3d4bf9b6a0a2ca1f961edfe9a9c0bcd722f34b14..e3339e41ddf7a30aea4e7d01b1e72aab67cf54e9 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1183,6 +1183,9 @@ struct intel_plane {
                           struct intel_plane_state *plane_state);
        int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
                         const struct intel_plane_state *plane_state);
+       void (*async_flip)(struct intel_plane *plane,
+                          const struct intel_crtc_state *crtc_state,
+                          const struct intel_plane_state *plane_state);
 };
 
 struct intel_watermark_params {

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 76a3d9bfe0dee27d336646debb4d80f37af2875d..d4b8ba7e8015c30961eba991bd5526579b634cce 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane,
                          PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
 }
 
+static void
+skl_plane_async_flip(struct intel_plane *plane,
+                    const struct intel_crtc_state *crtc_state,
+                    const struct intel_plane_state *plane_state)
+{
+       struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+       unsigned long irqflags;
+       enum plane_id plane_id = plane->id;
+       enum pipe pipe = plane->pipe;
+       u32 surf_addr = plane_state->color_plane[0].offset;
+       u32 plane_ctl = plane_state->ctl;
+
+       plane_ctl |= skl_plane_ctl_crtc(crtc_state);
+
+       spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+
+       intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
+       intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
+                         intel_plane_ggtt_offset(plane_state) + surf_addr);
+
+       spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
 static void
 skl_program_plane(struct intel_plane *plane,
                  const struct intel_crtc_state *crtc_state,
@@ -3095,6 +3118,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
        plane->get_hw_state = skl_plane_get_hw_state;
        plane->check_plane = skl_plane_check;
        plane->min_cdclk = skl_plane_min_cdclk;
+       plane->async_flip = skl_plane_async_flip;
 
        if (INTEL_GEN(dev_priv) >= 11)
                formats = icl_get_plane_formats(dev_priv, pipe,