feat(qemu): make coherent memory section optional

Since CPUs such as cortex-a76 are hardware-assisted coherent, coherent
memory section is not required for them and should be an optional
section.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I03c8e9148ca1780b8af92024359698f4452f7129

diff --git a/plat/qemu/common/qemu_bl1_setup.c b/plat/qemu/common/qemu_bl1_setup.c
index a3f61732d14bf13261c6b375a8c6a5bb7ea547a3..529510ce435637419aba9be57d9772ab6ca6f112 100644 (file)
--- a/plat/qemu/common/qemu_bl1_setup.c
+++ b/plat/qemu/common/qemu_bl1_setup.c
@@ -29,11 +29,13 @@
                                                - BL_RO_DATA_BASE,      \
                                        MT_RO_DATA | EL3_PAS)
 
+#if USE_COHERENT_MEM
 #define MAP_BL_COHERENT_RAM    MAP_REGION_FLAT(                        \
                                        BL_COHERENT_RAM_BASE,           \
                                        BL_COHERENT_RAM_END             \
                                                - BL_COHERENT_RAM_BASE, \
                                        MT_DEVICE | MT_RW | EL3_PAS)
+#endif
 
 /* Data structure which holds the extents of the trusted SRAM for BL1*/
 static meminfo_t bl1_tzram_layout;
@@ -73,7 +75,9 @@ void bl1_plat_arch_setup(void)
        const mmap_region_t bl_regions[] = {
                MAP_BL1_TOTAL,
                MAP_BL1_RO,
+#if USE_COHERENT_MEM
                MAP_BL_COHERENT_RAM,
+#endif
                {0}
        };
 

diff --git a/plat/qemu/common/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c
index 8f6066bb56722edb43ec610b42ca6fb3df0e5dfb..c4d235e0a0d7fd43bda25cfd68d10c05a32872bc 100644 (file)
--- a/plat/qemu/common/qemu_bl2_setup.c
+++ b/plat/qemu/common/qemu_bl2_setup.c
@@ -38,11 +38,13 @@
                                                - BL_RO_DATA_BASE,      \
                                        MT_RO_DATA | MT_SECURE)
 
+#if USE_COHERENT_MEM
 #define MAP_BL_COHERENT_RAM    MAP_REGION_FLAT(                        \
                                        BL_COHERENT_RAM_BASE,           \
                                        BL_COHERENT_RAM_END             \
                                                - BL_COHERENT_RAM_BASE, \
                                        MT_DEVICE | MT_RW | MT_SECURE)
+#endif
 
 /* Data structure which holds the extents of the trusted SRAM for BL2 */
 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
@@ -108,7 +110,9 @@ void bl2_plat_arch_setup(void)
        const mmap_region_t bl_regions[] = {
                MAP_BL2_TOTAL,
                MAP_BL2_RO,
+#if USE_COHERENT_MEM
                MAP_BL_COHERENT_RAM,
+#endif
                {0}
        };
 

diff --git a/plat/qemu/common/qemu_bl31_setup.c b/plat/qemu/common/qemu_bl31_setup.c
index 3195d9158dc46d3247175226c86a33154682d805..0b84e9620519456116acff0211afe845a63f87fa 100644 (file)
--- a/plat/qemu/common/qemu_bl31_setup.c
+++ b/plat/qemu/common/qemu_bl31_setup.c
@@ -26,11 +26,13 @@
                                                - BL_RO_DATA_BASE,      \
                                        MT_RO_DATA | EL3_PAS)
 
+#if USE_COHERENT_MEM
 #define MAP_BL_COHERENT_RAM    MAP_REGION_FLAT(                        \
                                        BL_COHERENT_RAM_BASE,           \
                                        BL_COHERENT_RAM_END             \
                                                - BL_COHERENT_RAM_BASE, \
                                        MT_DEVICE | MT_RW | EL3_PAS)
+#endif
 
 /*
  * Placeholder variables for copying the arguments that have been passed to
@@ -87,7 +89,9 @@ void bl31_plat_arch_setup(void)
        const mmap_region_t bl_regions[] = {
                MAP_BL31_TOTAL,
                MAP_BL31_RO,
+#if USE_COHERENT_MEM
                MAP_BL_COHERENT_RAM,
+#endif
                {0}
        };