drm/amdgpu: revise the mode2 reset for vangogh

PCIE MMIO bar needs to be restored firstly after the reset event
triggers. So it's unable to access the registers to wait for response
from SMU. Becasue the value of mmMP1_SMN_C2PMSG_90 is invalid at that
moment.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index e31033d38c2f063a3bd8b0bc4d23dfbf0b2eef96..a38433ed3a72ffc078e73c5b5ca42a25dcf495d4 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -1562,9 +1562,29 @@ static int vangogh_post_smu_init(struct smu_context *smu)
        }
 }
 
+static int vangogh_mode_reset(struct smu_context *smu, int type)
+{
+       int ret = 0, index = 0;
+
+       index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
+                                              SMU_MSG_GfxDeviceDriverReset);
+       if (index < 0)
+               return index == -EACCES ? 0 : index;
+
+       mutex_lock(&smu->message_lock);
+
+       ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
+
+       mutex_unlock(&smu->message_lock);
+
+       mdelay(10);
+
+       return ret;
+}
+
 static int vangogh_mode2_reset(struct smu_context *smu)
 {
-       return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);
+       return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
 }
 
 static const struct pptable_funcs vangogh_ppt_funcs = {

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index d7d86fd79e1ff98b2cb9b64ef0d6df0d2b7baf6d..11944d640ab0dcdfefbf483e49d434a2e5584530 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -68,14 +68,6 @@ static const char *smu_get_message_name(struct smu_context *smu,
        return __smu_message_names[type];
 }
 
-static void smu_cmn_send_msg_without_waiting(struct smu_context *smu,
-                                            uint16_t msg)
-{
-       struct amdgpu_device *adev = smu->adev;
-
-       WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
-}
-
 static void smu_cmn_read_arg(struct smu_context *smu,
                             uint32_t *arg)
 {
@@ -104,6 +96,28 @@ static int smu_cmn_wait_for_response(struct smu_context *smu)
        return RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90);
 }
 
+int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
+                                    uint16_t msg, uint32_t param)
+{
+       struct amdgpu_device *adev = smu->adev;
+       int ret;
+
+       ret = smu_cmn_wait_for_response(smu);
+       if (ret != 0x1) {
+               dev_err(adev->dev, "Msg issuing pre-check failed and "
+                      "SMU may be not in the right state!\n");
+               if (ret != -ETIME)
+                       ret = -EIO;
+               return ret;
+       }
+
+       WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+       WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
+       WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
+
+       return 0;
+}
+
 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
                                    enum smu_message_type msg,
                                    uint32_t param,
@@ -122,20 +136,9 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
                return index == -EACCES ? 0 : index;
 
        mutex_lock(&smu->message_lock);
-       ret = smu_cmn_wait_for_response(smu);
-       if (ret != 0x1) {
-               dev_err(adev->dev, "Msg issuing pre-check failed and "
-                      "SMU may be not in the right state!\n");
-               if (ret != -ETIME)
-                       ret = -EIO;
+       ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, param);
+       if (ret)
                goto out;
-       }
-
-       WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
-
-       WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
-
-       smu_cmn_send_msg_without_waiting(smu, (uint16_t)index);
 
        ret = smu_cmn_wait_for_response(smu);
        if (ret != 0x1) {

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
index 01e825d83d8df87c59b1ef39afa1eae6d15b0a1f..08ccf2d3257cef697bf1583aab1ada3fee9658ca 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
@@ -26,6 +26,8 @@
 #include "amdgpu_smu.h"
 
 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4)
+int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
+                                    uint16_t msg, uint32_t param);
 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
                                    enum smu_message_type msg,
                                    uint32_t param,