feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles

The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency here for all A72 cores.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I639091dd0d2de09572bf0f73ac404e306e336883

diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h
index 4b1af61ca3f243275b338f79b6afe24b584acca5..c77484026f872710b6d244e08d37c8d91507258f 100644 (file)
--- a/include/lib/cpus/aarch32/cortex_a72.h
+++ b/include/lib/cpus/aarch32/cortex_a72.h
@@ -47,6 +47,7 @@
 #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT                U(6)
 
 #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES                U(0x2)
+#define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES                U(0x3)
 #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES         U(0x1)
 #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES         U(0x2)
 

diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index 17776458b825280786e192a4a39875e1274c2224..a666617f96775c39308bfda3d02f3706b2da5087 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -68,6 +68,7 @@
 #define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK            U(0x7)
 #define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK             U(0x7)
 #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES                U(0x2)
+#define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES                U(0x3)
 #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES         U(0x1)
 #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES         U(0x2)
 

diff --git a/plat/ti/k3/board/j784s4/board.mk b/plat/ti/k3/board/j784s4/board.mk
index 92433ab65844b37bceaee35c493c266a8db6df19..c7fcb00160341bee33b4aba319856542448729a6 100644 (file)
--- a/plat/ti/k3/board/j784s4/board.mk
+++ b/plat/ti/k3/board/j784s4/board.mk
@@ -17,6 +17,10 @@ $(eval $(call add_define,K3_HW_CONFIG_BASE))
 K3_SEC_PROXY_LITE      :=      0
 $(eval $(call add_define,K3_SEC_PROXY_LITE))
 
+# Use a 4 cycle data RAM latency for J784s4
+K3_DATA_RAM_4_LATENCY  :=      1
+$(eval $(call add_define,K3_DATA_RAM_4_LATENCY))
+
 # System coherency is managed in hardware
 USE_COHERENT_MEM       :=      1
 

diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S
index f4f7d18eacdda9f57ee68ba7915f62b8f8a33975..cc9934c4e9343e31f2d8851e8063c896eacf3dd5 100644 (file)
--- a/plat/ti/k3/common/k3_helpers.S
+++ b/plat/ti/k3/common/k3_helpers.S
@@ -105,7 +105,15 @@ func plat_reset_handler
        /* Cortex-A72 specific settings */
 a72:
        mrs x0, CORTEX_A72_L2CTLR_EL1
-       orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+#if K3_DATA_RAM_4_LATENCY
+       /* Set L2 cache data RAM latency to 4 cycles */
+       orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES << \
+                       CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+#else
+       /* Set L2 cache data RAM latency to 3 cycles */
+       orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << \
+                       CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+#endif
        msr CORTEX_A72_L2CTLR_EL1, x0
        isb
        ret