]> git.baikalelectronics.ru Git - kernel.git/commitdiff
drm/i915: Fix CHV DSI PLL refclk during state readout
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 15 Mar 2016 14:40:05 +0000 (16:40 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 12 Apr 2016 18:12:02 +0000 (21:12 +0300)
Use the proper refclock frequency (100MHz) when reading out the
current DSI clock on CHV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1458052809-23426-13-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/intel_dsi_pll.c

index bd17465018f4fc78cf63f332175f88d5988c8680..7ad59d13dd4cbc62ce410d0fef1d0bc3cb9cd47c 100644 (file)
@@ -258,7 +258,7 @@ static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp)
        u32 dsi_clock, pclk;
        u32 pll_ctl, pll_div;
        u32 m = 0, p = 0, n;
-       int refclk = 25000;
+       int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;
        int i;
 
        DRM_DEBUG_KMS("\n");