#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-#define IOX_SDI IMX_GPIO_NR(5, 10)
-#define IOX_STCP IMX_GPIO_NR(5, 7)
-#define IOX_SHCP IMX_GPIO_NR(5, 11)
-#define IOX_OE IMX_GPIO_NR(5, 8)
-
-static iomux_v3_cfg_t const iox_pads[] = {
- /* IOX_SDI */
- MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* IOX_SHCP */
- MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* IOX_STCP */
- MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* IOX_nOE */
- MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-/*
- * HDMI_nRST --> Q0
- * ENET1_nRST --> Q1
- * ENET2_nRST --> Q2
- * CAN1_2_STBY --> Q3
- * BT_nPWD --> Q4
- * CSI_RST --> Q5
- * CSI_PWDN --> Q6
- * LCD_nPWREN --> Q7
- */
-enum qn {
- HDMI_NRST,
- ENET1_NRST,
- ENET2_NRST,
- CAN1_2_STBY,
- BT_NPWD,
- CSI_RST,
- CSI_PWDN,
- LCD_NPWREN,
-};
-
-enum qn_func {
- qn_reset,
- qn_enable,
- qn_disable,
-};
-
-enum qn_level {
- qn_low = 0,
- qn_high = 1,
-};
-
-static enum qn_level seq[3][2] = {
- {0, 1}, {1, 1}, {0, 0}
-};
-
-static enum qn_func qn_output[8] = {
- qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
- qn_disable, qn_disable
-};
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-static void iox74lv_init(void)
+#ifdef CONFIG_DM_PMIC
+int power_init_board(void)
{
- int i;
+ struct udevice *dev;
+ int ret, dev_id, rev_id;
+ unsigned int reg;
+
+ ret = pmic_get("pfuze3000", &dev);
+ if (ret == -ENODEV)
+ return 0;
+ if (ret != 0)
+ return ret;
- gpio_direction_output(IOX_OE, 0);
+ dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+ rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
+ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
- for (i = 7; i >= 0; i--) {
- gpio_direction_output(IOX_SHCP, 0);
- gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
- udelay(500);
- gpio_direction_output(IOX_SHCP, 1);
- udelay(500);
- }
+ /* disable Low Power Mode during standby mode */
+ reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
+ reg |= 0x1;
+ pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
- gpio_direction_output(IOX_STCP, 0);
- udelay(500);
- /*
- * shift register will be output to pins
- */
- gpio_direction_output(IOX_STCP, 1);
-
- for (i = 7; i >= 0; i--) {
- gpio_direction_output(IOX_SHCP, 0);
- gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
- udelay(500);
- gpio_direction_output(IOX_SHCP, 1);
- udelay(500);
- }
- gpio_direction_output(IOX_STCP, 0);
- udelay(500);
- /*
- * shift register will be output to pins
- */
- gpio_direction_output(IOX_STCP, 1);
-};
+ /* SW1B step ramp up time from 2us to 4us/25mV */
+ reg = 0x40;
+ pmic_reg_write(dev, PFUZE3000_SW1BCONF, reg);
-#ifdef CONFIG_SYS_I2C_MXC
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C1 for PMIC and EEPROM */
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
- .gp = IMX_GPIO_NR(1, 28),
- },
- .sda = {
- .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
- .gp = IMX_GPIO_NR(1, 29),
- },
-};
+ /* SW1B mode to APS/PFM */
+ reg = 0xc;
+ pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
-#ifdef CONFIG_POWER
-#define I2C_PMIC 0
-int power_init_board(void)
-{
- if (is_mx6ul_9x9_evk()) {
- struct pmic *pfuze;
- int ret;
- unsigned int reg, rev_id;
-
- ret = power_pfuze3000_init(I2C_PMIC);
- if (ret)
- return ret;
-
- pfuze = pmic_get("PFUZE3000");
- ret = pmic_probe(pfuze);
- if (ret)
- return ret;
-
- pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®);
- pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
- printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n",
- reg, rev_id);
-
- /* disable Low Power Mode during standby mode */
- pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1);
-
- /* SW1B step ramp up time from 2us to 4us/25mV */
- reg = 0x40;
- pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
-
- /* SW1B mode to APS/PFM */
- reg = 0xc;
- pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
-
- /* SW1B standby voltage set to 0.975V */
- reg = 0xb;
- pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
- }
+ /* SW1B standby voltage set to 0.975V */
+ reg = 0xb;
+ pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
return 0;
}
#endif
-#endif
int dram_init(void)
{
}
#ifdef CONFIG_FSL_QSPI
-
-#define QSPI_PAD_CTRL1 \
- (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
- PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
-
-static iomux_v3_cfg_t const quadspi_pads[] = {
- MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-};
-
static int board_qspi_init(void)
{
- /* Set the iomux */
- imx_iomux_v3_setup_multiple_pads(quadspi_pads,
- ARRAY_SIZE(quadspi_pads));
/* Set the clock */
enable_qspi_clk(0);
ret = 1;
#else
imx_iomux_v3_setup_pad(usdhc2_cd_pad);
+ gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
gpio_direction_input(USDHC2_CD_GPIO);
/*
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
#endif
+ gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
gpio_direction_output(USDHC2_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC2_PWR_GPIO, 1);
#endif
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
static iomux_v3_cfg_t const usb_otg_pads[] = {
- MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
};
/* At default the 3v3 enables the MIC2026 for VBUS power */
return 0;
}
#endif
+#endif
#ifdef CONFIG_FEC_MXC
/*
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
/* Reset the LCD */
+ gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
udelay(500);
gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
/* Set Brightness to high */
+ gpio_request(IMX_GPIO_NR(1, 8), "backlight");
gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
return 0;
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
-
- iox74lv_init();
-
-#ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-#endif
-
#ifdef CONFIG_FEC_MXC
setup_fec(CONFIG_FEC_ENET_DEV);
#endif
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
setup_usb();
#endif
+#endif
#ifdef CONFIG_FSL_QSPI
board_qspi_init();
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