net: ethernet: mtk_eth_soc: Fix packet statistics support for MT7628/88

The MT7628/88 SoC(s) have other (limited) packet counter registers than
currently supported in the mtk_eth_soc driver. This patch adds support
for reading these registers, so that the packet statistics are correctly
updated.

Additionally the defines for the non-MT7628 variant packet counter
registers are added and used in this patch instead of using hard coded
values.

Signed-off-by: Stefan Roese <sr@denx.de>
Fixes: 296c9120752b ("net: ethernet: mediatek: Add MT7628/88 SoC support")
Cc: Felix Fietkau <nbd@nbd.name>
Cc: John Crispin <john@phrozen.org>
Cc: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Cc: Reto Schneider <code@reto-schneider.ch>
Cc: Reto Schneider <reto.schneider@husqvarnagroup.com>
Cc: David S. Miller <davem@davemloft.net>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index d6cc06ee0caa51abd86c03a86ecced009bfb3772..64adfd24e134d80ec341cf2ed5055e054ecc9b57 100644 (file)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -681,32 +681,53 @@ static int mtk_set_mac_address(struct net_device *dev, void *p)
 void mtk_stats_update_mac(struct mtk_mac *mac)
 {
        struct mtk_hw_stats *hw_stats = mac->hw_stats;
-       unsigned int base = MTK_GDM1_TX_GBCNT;
-       u64 stats;
-
-       base += hw_stats->reg_offset;
+       struct mtk_eth *eth = mac->hw;
 
        u64_stats_update_begin(&hw_stats->syncp);
 
-       hw_stats->rx_bytes += mtk_r32(mac->hw, base);
-       stats =  mtk_r32(mac->hw, base + 0x04);
-       if (stats)
-               hw_stats->rx_bytes += (stats << 32);
-       hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
-       hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
-       hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
-       hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
-       hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
-       hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
-       hw_stats->rx_flow_control_packets +=
-                                       mtk_r32(mac->hw, base + 0x24);
-       hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
-       hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
-       hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
-       stats =  mtk_r32(mac->hw, base + 0x34);
-       if (stats)
-               hw_stats->tx_bytes += (stats << 32);
-       hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
+       if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
+               hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT);
+               hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT);
+               hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT);
+               hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT);
+               hw_stats->rx_checksum_errors +=
+                       mtk_r32(mac->hw, MT7628_SDM_CS_ERR);
+       } else {
+               unsigned int offs = hw_stats->reg_offset;
+               u64 stats;
+
+               hw_stats->rx_bytes += mtk_r32(mac->hw,
+                                             MTK_GDM1_RX_GBCNT_L + offs);
+               stats = mtk_r32(mac->hw, MTK_GDM1_RX_GBCNT_H + offs);
+               if (stats)
+                       hw_stats->rx_bytes += (stats << 32);
+               hw_stats->rx_packets +=
+                       mtk_r32(mac->hw, MTK_GDM1_RX_GPCNT + offs);
+               hw_stats->rx_overflow +=
+                       mtk_r32(mac->hw, MTK_GDM1_RX_OERCNT + offs);
+               hw_stats->rx_fcs_errors +=
+                       mtk_r32(mac->hw, MTK_GDM1_RX_FERCNT + offs);
+               hw_stats->rx_short_errors +=
+                       mtk_r32(mac->hw, MTK_GDM1_RX_SERCNT + offs);
+               hw_stats->rx_long_errors +=
+                       mtk_r32(mac->hw, MTK_GDM1_RX_LENCNT + offs);
+               hw_stats->rx_checksum_errors +=
+                       mtk_r32(mac->hw, MTK_GDM1_RX_CERCNT + offs);
+               hw_stats->rx_flow_control_packets +=
+                       mtk_r32(mac->hw, MTK_GDM1_RX_FCCNT + offs);
+               hw_stats->tx_skip +=
+                       mtk_r32(mac->hw, MTK_GDM1_TX_SKIPCNT + offs);
+               hw_stats->tx_collisions +=
+                       mtk_r32(mac->hw, MTK_GDM1_TX_COLCNT + offs);
+               hw_stats->tx_bytes +=
+                       mtk_r32(mac->hw, MTK_GDM1_TX_GBCNT_L + offs);
+               stats =  mtk_r32(mac->hw, MTK_GDM1_TX_GBCNT_H + offs);
+               if (stats)
+                       hw_stats->tx_bytes += (stats << 32);
+               hw_stats->tx_packets +=
+                       mtk_r32(mac->hw, MTK_GDM1_TX_GPCNT + offs);
+       }
+
        u64_stats_update_end(&hw_stats->syncp);
 }
 

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 11331b44ba07966ee3baef60da719c1343dfc4df..5ef70dd8b49c655c8d954f96b0fb9c0228d94489 100644 (file)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -278,8 +278,21 @@
 /* QDMA FQ Free Page Buffer Length Register */
 #define MTK_QDMA_FQ_BLEN       0x1B2C
 
-/* GMA1 Received Good Byte Count Register */
-#define MTK_GDM1_TX_GBCNT      0x2400
+/* GMA1 counter / statics register */
+#define MTK_GDM1_RX_GBCNT_L    0x2400
+#define MTK_GDM1_RX_GBCNT_H    0x2404
+#define MTK_GDM1_RX_GPCNT      0x2408
+#define MTK_GDM1_RX_OERCNT     0x2410
+#define MTK_GDM1_RX_FERCNT     0x2414
+#define MTK_GDM1_RX_SERCNT     0x2418
+#define MTK_GDM1_RX_LENCNT     0x241c
+#define MTK_GDM1_RX_CERCNT     0x2420
+#define MTK_GDM1_RX_FCCNT      0x2424
+#define MTK_GDM1_TX_SKIPCNT    0x2428
+#define MTK_GDM1_TX_COLCNT     0x242c
+#define MTK_GDM1_TX_GBCNT_L    0x2430
+#define MTK_GDM1_TX_GBCNT_H    0x2434
+#define MTK_GDM1_TX_GPCNT      0x2438
 #define MTK_STAT_OFFSET                0x40
 
 /* QDMA descriptor txd4 */
@@ -502,6 +515,13 @@
 #define MT7628_SDM_MAC_ADRL    (MT7628_SDM_OFFSET + 0x0c)
 #define MT7628_SDM_MAC_ADRH    (MT7628_SDM_OFFSET + 0x10)
 
+/* Counter / stat register */
+#define MT7628_SDM_TPCNT       (MT7628_SDM_OFFSET + 0x100)
+#define MT7628_SDM_TBCNT       (MT7628_SDM_OFFSET + 0x104)
+#define MT7628_SDM_RPCNT       (MT7628_SDM_OFFSET + 0x108)
+#define MT7628_SDM_RBCNT       (MT7628_SDM_OFFSET + 0x10c)
+#define MT7628_SDM_CS_ERR      (MT7628_SDM_OFFSET + 0x110)
+
 struct mtk_rx_dma {
        unsigned int rxd1;
        unsigned int rxd2;