.align 3
.global __real_cntfrq
__real_cntfrq:
- .quad COUNTER_FREQUENCY
+ .quad CONFIG_COUNTER_FREQUENCY
/* Secondary Boot Code ends here */
__secondary_boot_code_end:
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 8000000 /* 8MHz */
-
#endif /* __APALIS_IMX8_H */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 8000000 /* 8MHz */
-
/* Networking */
#define CONFIG_FEC_ENET_DEV 0
#define IMX_FEC_BASE 0x5b040000
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 8000000 /* 8MHz */
-
#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 8000000 /* 8MHz */
-
/* Networking */
#define CONFIG_FEC_MXC_PHYADDR -1
#define FEC_QUIRK_ENET_MAC
sizeof(CONFIG_SYS_PROMPT) + 16)
/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 8000000 /* 8MHz */
#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
-/* Generic Timer Definitions (use in assembler source) */
-#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
-
#endif /* __CONDOR_H */
#include "rcar-gen3-common.h"
-/* Generic Timer Definitions (use in assembler source) */
-#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_FLASH_SHOW_PROGRESS 45
/* UART */
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 19000000
-
/* Fixup - in init code we switch from device to host mode,
* it has to be done after each HCD reset */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
#define CONFIG_SYS_BOOTM_LEN SZ_64M
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 19000000
-
#ifndef CONFIG_SPL_BUILD
#include <config_distro_bootcmd.h>
#endif
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
-/* Generic Timer Definitions (use in assembler source) */
-#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
-
#endif /* __EAGLE_H */
#include "rcar-gen3-common.h"
-/* Generic Timer Definitions (use in assembler source) */
-#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_FLASH_SHOW_PROGRESS 45
/* Keep L2 Cache Disabled */
/* input clock of PLL: 24MHz input clock */
-#define COUNTER_FREQUENCY 24000000
/* select serial console configuration */
/* select serial console configuration */
-/* Timer input clock frequency */
-#define COUNTER_FREQUENCY 24000000
-
/* IRAM Layout */
#define CONFIG_IRAM_BASE 0x02100000
#define CONFIG_IRAM_SIZE 0x58000
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/* Timer input clock frequency */
-#define COUNTER_FREQUENCY 26000000
-
#define CPU_RELEASE_ADDR secondary_boot_addr
#define CONFIG_SYS_BAUDRATE_TABLE \
/* Board Clock */
/* XTAL_CLK : 16.66MHz */
-/* Generic Timer Definitions (use in assembler source) */
-#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
-
#endif /* __FALCON_H */
#include "rcar-gen3-common.h"
-/* Generic Timer Definitions (use in assembler source) */
-#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
-
#endif /* __HIHOPE_RZG2_H */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 19000000
-
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0xf6801000
#define GICC_BASE 0xf6802000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 19000000
-
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0xe82b1000
#define GICC_BASE 0xe82b2000
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 8000000 /* 8MHz */
-
#endif /* __IMX8QM_MEK_H */
/* LPDDR4 board total DDR is 6GB, DDR4 board total DDR is 4 GB */
#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 8000000 /* 8MHz */
-
#include <linux/stringify.h>
#endif /* __IMX8QM_ROM7720_H */
/* LPDDR4 board total DDR is 3GB */
#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 8000000 /* 8MHz */
-
#ifndef CONFIG_DM_PCA953X
#define CONFIG_PCA953X
#endif
#endif
-#define COUNTER_FREQUENCY 1000000 /* 1MHz */
-
/* ENET Config */
#if defined(CONFIG_FEC_MXC)
#define PHY_ANEG_TIMEOUT 20000
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
-#define COUNTER_FREQUENCY 8333333
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 256
#define CPU_RELEASE_ADDR secondary_boot_addr
/* generic timer */
-#define COUNTER_FREQUENCY 25000000
/* early heap for SPL DM */
#define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-
/* CSU */
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
-#define COUNTER_FREQUENCY 12500000
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 256
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
-#define COUNTER_FREQUENCY 12500000
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 256
#endif
#define CONFIG_LAYERSCAPE_NS_ACCESS
-#define COUNTER_FREQUENCY 12500000
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 256
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
-#define COUNTER_FREQUENCY 12500000
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 256
*/
#define CPU_RELEASE_ADDR secondary_boot_addr
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-
/* GPIO */
/* I2C */
#define CPU_RELEASE_ADDR secondary_boot_addr
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CPU_RELEASE_ADDR secondary_boot_addr
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#endif
#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
-#define COUNTER_FREQUENCY 25000000 /* 25MHz */
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x51
#endif
#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
-#define COUNTER_FREQUENCY 25000000 /* 25MHz */
#ifdef CONFIG_EMU
#define CONFIG_SYS_FSL_DDR_EMU
#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
-/* Generic Timer Definitions */
/*
* This is not an accurate number. It is used in start.S. The frequency
* will be udpated later when get_bus_freq(0) is available.
*/
-#define COUNTER_FREQUENCY 25000000 /* 25MHz */
/* GPIO */
* will be udpated later when get_bus_freq(0) is available.
*/
-#define COUNTER_FREQUENCY 25000000 /* 25MHz */
/* Serial Port */
#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
#include <linux/sizes.h>
-#define COUNTER_FREQUENCY 13000000
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
-#define COUNTER_FREQUENCY 13000000
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#include <linux/sizes.h>
-#define COUNTER_FREQUENCY 13000000
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
-#define COUNTER_FREQUENCY 13000000
/* DRAM definition */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
-#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK
#else
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
/* Timer settings */
#define CONFIG_MXC_GPT_HCLK
#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
-#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK
#define CONFIG_SYS_BOOTM_LEN 0x1000000
/* SDRAM Definitions */
#define CONFIG_SYS_SDRAM_BASE 0x0
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY (24000000) /* 24MHz */
-
/* Some commands use this as the default load address */
/*
#include "tegra-common-post.h"
-/* Crystal is 38.4MHz. clk_m runs at half that rate */
-#define COUNTER_FREQUENCY 19200000
-
#endif /* _P2371_2180_H */
#include "tegra-common-post.h"
-/* Crystal is 38.4MHz. clk_m runs at half that rate */
-#define COUNTER_FREQUENCY 19200000
-
#endif
/* General networking support */
#include "tegra-common-post.h"
-/* Crystal is 38.4MHz. clk_m runs at half that rate */
-#define COUNTER_FREQUENCY 19200000
-
#endif /* _P3450_0000_H */
#define CONFIG_SYS_BOOTM_LEN 0x00c00000
/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 25000000
-#define CONFIG_SYS_TIMER_RATE COUNTER_FREQUENCY
+#define CONFIG_SYS_TIMER_RATE 25000000
#define CONFIG_SYS_TIMER_COUNTER 0xf4321008
/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
#define CONFIG_SYS_NS16550_MEM32
-#define COUNTER_FREQUENCY 24000000
-
/* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */
#define CONFIG_IRAM_BASE 0xff020000
#define CONFIG_SYS_CBSIZE 1024
-#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_CBSIZE 1024
-#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_IRAM_BASE 0x10080000
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
-#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_SYS_INIT_SP_ADDR 0x61100000
#define CONFIG_SYS_CBSIZE 1024
-#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_HZ_CLOCK 24000000
#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
#define CONFIG_SPL_STACK 0x00400000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
-#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#define CONFIG_IRAM_BASE 0xff090000
-#define COUNTER_FREQUENCY 24000000
-
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
#define SDRAM_MAX_SIZE 0xff000000
#define CONFIG_SYS_CBSIZE 1024
-#define COUNTER_FREQUENCY 24000000
-
#define CONFIG_IRAM_BASE 0xff8c0000
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
#define CONFIG_SYS_CBSIZE 1024
-#define COUNTER_FREQUENCY 24000000
-
#define CONFIG_IRAM_BASE 0xff8c0000
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
#define CONFIG_SYS_CBSIZE 1024
-#define COUNTER_FREQUENCY 24000000
-
#define CONFIG_IRAM_BASE 0xfdcc0000
#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
#include "rcar-gen3-common.h"
-/* Generic Timer Definitions (use in assembler source) */
-#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 19000000
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x4000000\0" \
"bootm_low=0x80000000\0" \
#include "rcar-gen3-common.h"
-/* Generic Timer Definitions (use in assembler source) */
-#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
-
#endif /* __SILINUX_EK874_H */
#define CONFIG_SYS_NS16550_CLK 100000000
#define CONFIG_SYS_NS16550_MEM32
-/*
- * Timer & watchdog configurations
- */
-#define COUNTER_FREQUENCY 400000000
-
/*
* SDMMC configurations
*/
#endif
/* CPU */
-#define COUNTER_FREQUENCY 24000000
/*
* The DRAM Base differs between some models. We cannot use macros for the
#include "ls1088a_common.h"
-#define COUNTER_FREQUENCY 25000000 /* 25MHz */
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
/* SMP Spin Table Definitions */
#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
-
/* PL011 Serial Configuration */
#define CONFIG_PL011_CLOCK 24000000
#include "rcar-gen3-common.h"
-/* Generic Timer Definitions (use in assembler source) */
-#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 24000000 /* 24MHz */
-
/* Generic Interrupt Controller Definitions */
#ifdef CONFIG_GICV3
#define GICD_BASE (V2M_PA_BASE + 0x2f000000)
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
-/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
-#if CONFIG_COUNTER_FREQUENCY
-# define COUNTER_FREQUENCY CONFIG_COUNTER_FREQUENCY
-#endif
-
/* Serial setup */
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 4800, 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
-/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
-#if !defined(COUNTER_FREQUENCY)
-# define COUNTER_FREQUENCY 100000000
-#endif
-
/* Serial setup */
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 4800, 9600, 19200, 38400, 57600, 115200 }
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