drm/amd/display: Dynamic cursor cache size for MALL eligibility check

[Why]
Currently we use the maximum possible cursor cache size when deciding if we
should attempt to enable MALL, but this prevents us from enabling the
feature for certain key use cases.

[How]
 - consider cursor bpp when calculating if the cursor fits

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 89e8e3e11862c352c5cc7ed108d294ef25147eb9..1efc67befad4bec11286082353a8675a26001112 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3156,11 +3156,11 @@ void dc_lock_memory_clock_frequency(struct dc *dc)
                        core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
 }
 
-bool dc_is_plane_eligible_for_idle_optimizaitons(struct dc *dc, struct dc_plane_state *plane)
+bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
+               struct dc_cursor_attributes *cursor_attr)
 {
-       if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane))
+       if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane, cursor_attr))
                return true;
-
        return false;
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 28e0b6ac1f50ec39329cd86bf17c24b7ed330b14..e21d4602e42788b0b993f816f1a6b0596ff4a6a9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1272,8 +1272,8 @@ enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32
 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 
-bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,
-                                                struct dc_plane_state *plane);
+bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
+                               struct dc_cursor_attributes *cursor_attr);
 
 void dc_allow_idle_optimizations(struct dc *dc, bool allow);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index e5cc8f8c363f34a9edf544a1ef843789823af7e1..5c546b06f5510a484588c015d42a28cca736b9da 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -814,17 +814,38 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
        return true;
 }
 
-bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane)
+bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_attributes *cursor_attr)
 {
        // add meta size?
        unsigned int surface_size = plane->plane_size.surface_pitch * plane->plane_size.surface_size.height *
                        (plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
        unsigned int mall_size = dc->caps.mall_size_total;
+       unsigned int cursor_size = 0;
 
        if (dc->debug.mall_size_override)
                mall_size = 1024 * 1024 * dc->debug.mall_size_override;
 
-       return (surface_size + dc->caps.cursor_cache_size) < mall_size;
+       if (cursor_attr) {
+               cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
+
+               switch (cursor_attr->color_format) {
+               case CURSOR_MODE_MONO:
+                       cursor_size /= 2;
+                       break;
+               case CURSOR_MODE_COLOR_1BIT_AND:
+               case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
+               case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
+                       cursor_size *= 4;
+                       break;
+
+               case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
+               case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
+                       cursor_size *= 8;
+                       break;
+               }
+       }
+
+       return (surface_size + cursor_size) < mall_size;
 }
 
 void dcn30_hardware_release(struct dc *dc)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
index 1103f6356e901d15bfb4ef492537be62f116d348..3b7d4812e3119b1008f081f8da156a2aa6318c1a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
@@ -65,7 +65,8 @@ void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
 void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);
 void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
 
-bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane);
+bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane,
+               struct dc_cursor_attributes *cursor_attr);
 
 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index 22ba0be88fafd912f468eca66fd1134713f8efb3..b96b32a37178a9528b0a7e5db4f1a36694b55afa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -1317,6 +1317,7 @@ static bool dcn302_resource_construct(
        dc->caps.min_horizontal_blanking_period = 80;
        dc->caps.dmdata_alloc_size = 2048;
 
+       dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
        dc->caps.max_slave_planes = 1;
        dc->caps.post_blend_color_processing = true;
        dc->caps.force_dp_tps4_for_cp2520 = true;

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 48378beb71c0fb19d408d1ad7a58aa2a176c6346..0586ab2ffd6ab46d9001f0ed9fa0cdc244676f7e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -218,7 +218,8 @@ struct hw_sequencer_funcs {
        /* Idle Optimization Related */
        bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable);
 
-       bool (*does_plane_fit_in_mall)(struct dc *dc, struct dc_plane_state *plane);
+       bool (*does_plane_fit_in_mall)(struct dc *dc, struct dc_plane_state *plane,
+                       struct dc_cursor_attributes *cursor_attr);
 
        bool (*is_abm_supported)(struct dc *dc,
                        struct dc_state *context, struct dc_stream_state *stream);