* claimed. This way, the dummy CS is restored to its inactive value when
* transfers are issued and the desired CS is preserved in its active value
* all the time. This hack is also used in the upstream linux driver and
- * allows keeping CS active between trasnfers even if the HW doesn't give
+ * allows keeping CS active between transfers even if the HW doesn't give
* this possibility.
*/
static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
plat->is_dma = dev_read_bool(bus, "cdns,is-dma");
- /* All other paramters are embedded in the child node */
+ /* All other parameters are embedded in the child node */
subnode = dev_read_first_subnode(bus);
if (!ofnode_valid(subnode)) {
printf("Error: subnode with SPI flash config missing!\n");
dm_spi_bus = dev_get_uclass_priv(bus);
- /* cpu speical pin muxing configure */
+ /* cpu special pin muxing configure */
cpu_dspi_port_conf();
/* get input clk frequency */
plat->speed_hz = fdtdec_get_int(blob,
node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
- debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n",
+ debug("DSPI: regs=%pa, max-frequency=%d, endianness=%s, num-cs=%d\n",
&plat->regs_addr, plat->speed_hz,
plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
plat->num_chipselect);
/*
* The output data will always be copied to the beginning of
- * the GPRAM. Uses word write for better performace.
+ * the GPRAM. Uses word write for better performance.
*
* Trailing bytes in the last word are not cared.
*/
/*
* Read aligned data from GPRAM to buffer first.
- * Uses word read for better performace.
+ * Uses word read for better performance.
*/
i = 0;
while (pos < end) {
* The XFER_RDY flag is checked every time before accessing SPI_DOUT
* and SPI_DIN register.
*
- * The number of transfers to be triggerred is decided by @bytelen.
+ * The number of transfers to be triggered is decided by @bytelen.
*
* Return: 0 - cool
* -ETIMEDOUT - XFER_RDY flag timeout
}
}
- /* Disable the channel to prevent furher receiving */
+ /* Disable the channel to prevent further receiving */
if (i == (len - 1))
omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
/*
* In case that there's a transmit-component, we need to wait
* until the control goes idle before we can disable the SPI
- * control logic (as this will implictly flush the FIFOs).
+ * control logic (as this will implicitly flush the FIFOs).
*/
if (out) {
ret = rkspi_wait_till_not_busy(regs);
flashes[cs].ahb_decoded_sz = priv->info->min_decoded_sz;
/*
- * If commnad mode or normal mode is used, the start address of a
+ * If command mode or normal mode is used, the start address of a
* decoded range should be multiple of its related flash size.
* Namely, the total decoded size from flash 0 to flash N should
* be multiple of the size of flash (N + 1).
flashes[cs].ahb_decoded_sz = 0;
/*
- * If commnad mode or normal mode is used, the start address of a
+ * If command mode or normal mode is used, the start address of a
* decoded range should be multiple of its related flash size.
* Namely, the total decoded size from flash 0 to flash N should
* be multiple of the size of flash (N + 1).
}
/*
- * Function to check wheather Input or Output FIFO
+ * Function to check whether Input or Output FIFO
* has data to be serviced
*/
static int qup_spi_check_fifo_status(struct udevice *dev, u32 reg_addr)
if (speed > spi->freq)
speed = spi->freq;
- /* Cofigure max speed */
+ /* Configure max speed */
scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1)
& SIFIVE_SPI_SCKDIV_DIV_MASK;
writel(scale, spi->regs + SIFIVE_SPI_REG_SCKDIV);