*/
#include <dt-bindings/clock/bcm6348-clock.h>
+#include <dt-bindings/dma/bcm6348-dma.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/bcm6348-reset.h>
#include "skeleton.dtsi"
reg = <0xfffe2300 0x38>;
u-boot,dm-pre-reloc;
};
+
+ iudma: dma-controller@fffe7000 {
+ compatible = "brcm,bcm6348-iudma";
+ reg = <0xfffe7000 0x1c>,
+ <0xfffe7100 0x40>,
+ <0xfffe7200 0x40>;
+ reg-names = "dma",
+ "dma-channels",
+ "dma-sram";
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ clocks = <&periph_clk BCM6348_CLK_ENET>;
+ resets = <&periph_rst BCM6348_RST_ENET>,
+ <&periph_rst BCM6348_RST_DMAMEM>;
+ };
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+ */
+
+#ifndef __DT_BINDINGS_DMA_BCM6348_H
+#define __DT_BINDINGS_DMA_BCM6348_H
+
+#define BCM6348_DMA_ENET0_RX 0
+#define BCM6348_DMA_ENET0_TX 1
+#define BCM6348_DMA_ENET1_RX 2
+#define BCM6348_DMA_ENET1_TX 3
+
+#endif /* __DT_BINDINGS_DMA_BCM6348_H */