drm/amdgpu: Modify GC register access from MMIO to RLCG in file soc15.c

In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.

Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 75008cc5f189143e8ece912fdb884fb77053ec84..de85577c9cfde5c3061ed640012808107f49b69d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -633,7 +633,9 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,
                if (entry->and_mask == 0xffffffff) {
                        tmp = entry->or_mask;
                } else {
-                       tmp = RREG32(reg);
+                       tmp = (entry->hwip == GC_HWIP) ?
+                               RREG32_SOC15_IP(GC, reg) : RREG32(reg);
+
                        tmp &= ~(entry->and_mask);
                        tmp |= (entry->or_mask & entry->and_mask);
                }
@@ -644,7 +646,8 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,
                        reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
                        WREG32_RLC(reg, tmp);
                else
-                       WREG32(reg, tmp);
+                       (entry->hwip == GC_HWIP) ?
+                               WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
 
        }