#include <asm/io.h>
#include <asm/arch/nexell.h>
#include <asm/arch/clk.h>
-#include <asm/arch/reset.h>
#include <asm/arch/tieoff.h>
#include <cpu_func.h>
-#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1);
}
-#ifdef CONFIG_PL011_SERIAL
-static void serial_device_init(void)
-{
- char dev[10];
- int id;
-
- sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX);
- id = RESET_ID_UART0 + CONFIG_CONS_INDEX;
-
- struct clk *clk = clk_get((const char *)dev);
-
- /* reset control: Low active ___|--- */
- nx_rstcon_setrst(id, RSTCON_ASSERT);
- udelay(10);
- nx_rstcon_setrst(id, RSTCON_NEGATE);
- udelay(10);
-
- /* set clock */
- clk_disable(clk);
- clk_set_rate(clk, CFG_PL011_CLOCK);
- clk_enable(clk);
-}
-#endif
-
int arch_cpu_init(void)
{
flush_dcache_all();
cpu_soc_init();
clk_init();
- if (IS_ENABLED(CONFIG_PL011_SERIAL))
- serial_device_init();
-
return 0;
}
}
/* prevent uart clock disable for low step debug message */
- #ifndef CONFIG_DEBUG_NX_UART
+ #ifndef CONFIG_DEBUG_UART
if (peri->dev_name) {
#ifdef CONFIG_BACKLIGHT_PWM
if (!strcmp(peri->dev_name, DEV_NAME_PWM))
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="s5p4418-nanopi2"
CONFIG_SYS_PROMPT="nanopi2# "
+CONFIG_DEBUG_UART_BASE=0xC00A1000
+CONFIG_DEBUG_UART_CLOCK=150000000
CONFIG_TARGET_NANOPI2=y
CONFIG_S5P4418_ONEWIRE=y
CONFIG_ROOT_DEV=1
CONFIG_BOOT_PART=1
CONFIG_ROOT_PART=2
CONFIG_SYS_LOAD_ADDR=0x71080000
+CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x71000000
CONFIG_SYS_MEMTEST_END=0xb0000000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
-CONFIG_CONS_INDEX=0
+CONFIG_DEBUG_UART_PL011=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_DISPLAY=y
/*-----------------------------------------------------------------------
* serial console configuration
*/
-#define CFG_PL011_CLOCK 50000000
-#define CFG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \
- (void *)PHY_BASEADDR_UART1, \
- (void *)PHY_BASEADDR_UART2, \
- (void *)PHY_BASEADDR_UART3}
+
+/* 150MHz is the clock rate set by SPL (uart0) */
+#define CFG_PL011_CLOCK 150000000
/*-----------------------------------------------------------------------
* BACKLIGHT