]> git.baikalelectronics.ru Git - kernel.git/commitdiff
net/mlx5e: IPsec: Fix crypto offload for non TCP/UDP encapsulated traffic
authorRaed Salem <raeds@nvidia.com>
Thu, 2 Dec 2021 15:43:50 +0000 (17:43 +0200)
committerSaeed Mahameed <saeedm@nvidia.com>
Wed, 2 Feb 2022 04:59:42 +0000 (20:59 -0800)
IPsec crypto offload always set the ethernet segment checksum flags with
the inner L4 header checksum flag enabled for encapsulated IPsec offloaded
packet regardless of the encapsulated L4 header type, and even if it
doesn't exists in the first place, this breaks non TCP/UDP traffic as
such.

Set the inner L4 checksum flag only when the encapsulated L4 header
protocol is TCP/UDP using software parser swp_inner_l4_offset field as
indication.

Fixes: f76b91ff5d9a ("net/mlx5e: Set IPsec WAs only in IP's non checksum partial case.")
Signed-off-by: Raed Salem <raeds@nvidia.com>
Reviewed-by: Maor Dickman <maord@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h

index b98db50c3418d9daad27e5fcaa756c8126557265..428881e0adcbeae1d5d70a84c27427986958972e 100644 (file)
@@ -131,14 +131,17 @@ static inline bool
 mlx5e_ipsec_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb,
                                  struct mlx5_wqe_eth_seg *eseg)
 {
-       struct xfrm_offload *xo = xfrm_offload(skb);
+       u8 inner_ipproto;
 
        if (!mlx5e_ipsec_eseg_meta(eseg))
                return false;
 
        eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
-       if (xo->inner_ipproto) {
-               eseg->cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM | MLX5_ETH_WQE_L3_INNER_CSUM;
+       inner_ipproto = xfrm_offload(skb)->inner_ipproto;
+       if (inner_ipproto) {
+               eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM;
+               if (inner_ipproto == IPPROTO_TCP || inner_ipproto == IPPROTO_UDP)
+                       eseg->cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
        } else if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
                eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM;
                sq->stats->csum_partial_inner++;