}
static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
}
static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
}
static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
+icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (rate > 540000) {
+ if (crtc_state->port_clock > 540000) {
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
return icl_combo_phy_ddi_translations_edp_hbr3;
} else if (dev_priv->vbt.edp.low_vswing) {
return icl_combo_phy_ddi_translations_edp_hbr2;
}
- return icl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+ return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
}
static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
+icl_get_combo_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- if (type == INTEL_OUTPUT_HDMI)
- return icl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
- else if (type == INTEL_OUTPUT_EDP)
- return icl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+ return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
else
- return icl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+ return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
}
static const struct icl_mg_phy_ddi_buf_trans *
-icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
}
static const struct icl_mg_phy_ddi_buf_trans *
-icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+icl_get_mg_buf_trans_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- if (rate > 270000) {
+ if (crtc_state->port_clock > 270000) {
*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
return icl_mg_phy_ddi_translations_hbr2_hbr3;
} else {
}
static const struct icl_mg_phy_ddi_buf_trans *
-icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
+icl_get_mg_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- if (type == INTEL_OUTPUT_HDMI)
- return icl_get_mg_buf_trans_hdmi(encoder, type, rate, n_entries);
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return icl_get_mg_buf_trans_hdmi(encoder, crtc_state, n_entries);
else
- return icl_get_mg_buf_trans_dp(encoder, type, rate, n_entries);
+ return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries);
}
static const struct cnl_ddi_buf_trans *
-ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
}
static const struct cnl_ddi_buf_trans *
-ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
*n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
}
static const struct cnl_ddi_buf_trans *
-ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
+ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
if (dev_priv->vbt.edp.low_vswing) {
- if (rate > 540000) {
+ if (crtc_state->port_clock > 540000) {
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
return icl_combo_phy_ddi_translations_edp_hbr3;
} else {
}
}
- return ehl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+ return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
}
static const struct cnl_ddi_buf_trans *
-ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
+ehl_get_combo_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- if (type == INTEL_OUTPUT_HDMI)
- return ehl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
- else if (type == INTEL_OUTPUT_EDP)
- return ehl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return ehl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+ return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
else
- return ehl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+ return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
}
static const struct cnl_ddi_buf_trans *
-tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
}
static const struct cnl_ddi_buf_trans *
-tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (rate > 270000) {
+ if (crtc_state->port_clock > 270000) {
if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
*n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
}
static const struct cnl_ddi_buf_trans *
-tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
+tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- if (rate > 540000) {
+ if (crtc_state->port_clock > 540000) {
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
return icl_combo_phy_ddi_translations_edp_hbr3;
} else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
return icl_combo_phy_ddi_translations_edp_hbr2;
}
- return tgl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+ return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
}
static const struct cnl_ddi_buf_trans *
-tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
+tgl_get_combo_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- if (type == INTEL_OUTPUT_HDMI)
- return tgl_get_combo_buf_trans_hdmi(encoder, type, rate, n_entries);
- else if (type == INTEL_OUTPUT_EDP)
- return tgl_get_combo_buf_trans_edp(encoder, type, rate, n_entries);
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+ return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
else
- return tgl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+ return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
}
static const struct tgl_dkl_phy_ddi_buf_trans *
-tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
*n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
}
static const struct tgl_dkl_phy_ddi_buf_trans *
-tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- if (rate > 270000) {
+ if (crtc_state->port_clock > 270000) {
*n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2);
return tgl_dkl_phy_dp_ddi_trans_hbr2;
} else {
}
static const struct tgl_dkl_phy_ddi_buf_trans *
-tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
+tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- if (type == INTEL_OUTPUT_HDMI)
- return tgl_get_dkl_buf_trans_hdmi(encoder, type, rate, n_entries);
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries);
else
- return tgl_get_dkl_buf_trans_dp(encoder, type, rate, n_entries);
+ return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
}
-static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
+static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
int n_entries, level, default_entry;
if (INTEL_GEN(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
- tgl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
- 0, &n_entries);
+ tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
else
- tgl_get_dkl_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
- &n_entries);
+ tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries);
default_entry = n_entries - 1;
} else if (INTEL_GEN(dev_priv) == 11) {
if (intel_phy_is_combo(dev_priv, phy))
- icl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
- 0, &n_entries);
+ icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
else
- icl_get_mg_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
- &n_entries);
+ icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries);
default_entry = n_entries - 1;
} else if (IS_CANNONLAKE(dev_priv)) {
cnl_get_buf_trans_hdmi(encoder, &n_entries);
DP_TP_CTL_ENABLE);
}
-static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
+static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
intel_dp->DP = dig_port->saved_port_bits |
DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
- intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
+ intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
}
static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
}
static void skl_ddi_set_iboost(struct intel_encoder *encoder,
- int level, enum intel_output_type type)
+ const struct intel_crtc_state *crtc_state,
+ int level)
{
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u8 iboost;
- if (type == INTEL_OUTPUT_HDMI)
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
iboost = intel_bios_hdmi_boost_level(encoder);
else
iboost = intel_bios_dp_boost_level(encoder);
const struct ddi_buf_trans *ddi_translations;
int n_entries;
- if (type == INTEL_OUTPUT_HDMI)
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
- else if (type == INTEL_OUTPUT_EDP)
- ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
- &n_entries);
+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+ ddi_translations = intel_ddi_get_buf_trans_edp(encoder, &n_entries);
else
- ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
- &n_entries);
+ ddi_translations = intel_ddi_get_buf_trans_dp(encoder, &n_entries);
if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
return;
}
static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
- int level, enum intel_output_type type)
+ const struct intel_crtc_state *crtc_state,
+ int level)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
const struct bxt_ddi_buf_trans *ddi_translations;
enum port port = encoder->port;
int n_entries;
- if (type == INTEL_OUTPUT_HDMI)
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries);
- else if (type == INTEL_OUTPUT_EDP)
+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries);
else
ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries);
ddi_translations[level].deemphasis);
}
-static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
+static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
if (INTEL_GEN(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
- tgl_get_combo_buf_trans(encoder, encoder->type,
- intel_dp->link_rate, &n_entries);
+ tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
else
- tgl_get_dkl_buf_trans(encoder, encoder->type,
- intel_dp->link_rate, &n_entries);
+ tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
} else if (INTEL_GEN(dev_priv) == 11) {
if (IS_ELKHARTLAKE(dev_priv))
- ehl_get_combo_buf_trans(encoder, encoder->type,
- intel_dp->link_rate, &n_entries);
+ ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
else if (intel_phy_is_combo(dev_priv, phy))
- icl_get_combo_buf_trans(encoder, encoder->type,
- intel_dp->link_rate, &n_entries);
+ icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
else
- icl_get_mg_buf_trans(encoder, encoder->type,
- intel_dp->link_rate, &n_entries);
+ icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
} else if (IS_CANNONLAKE(dev_priv)) {
- if (encoder->type == INTEL_OUTPUT_EDP)
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
cnl_get_buf_trans_edp(encoder, &n_entries);
else
cnl_get_buf_trans_dp(encoder, &n_entries);
} else if (IS_GEN9_LP(dev_priv)) {
- if (encoder->type == INTEL_OUTPUT_EDP)
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
bxt_get_buf_trans_edp(encoder, &n_entries);
else
bxt_get_buf_trans_dp(encoder, &n_entries);
} else {
- if (encoder->type == INTEL_OUTPUT_EDP)
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
intel_ddi_get_buf_trans_edp(encoder, &n_entries);
else
intel_ddi_get_buf_trans_dp(encoder, &n_entries);
}
static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
- int level, enum intel_output_type type)
+ const struct intel_crtc_state *crtc_state,
+ int level)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
const struct cnl_ddi_buf_trans *ddi_translations;
int n_entries, ln;
u32 val;
- if (type == INTEL_OUTPUT_HDMI)
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries);
- else if (type == INTEL_OUTPUT_EDP)
+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries);
else
ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries);
}
static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
- int level, enum intel_output_type type)
+ const struct intel_crtc_state *crtc_state,
+ int level)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
int width, rate, ln;
u32 val;
- if (type == INTEL_OUTPUT_HDMI) {
- width = 4;
- rate = 0; /* Rate is always < than 6GHz for HDMI */
- } else {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- width = intel_dp->lane_count;
- rate = intel_dp->link_rate;
- }
+ width = crtc_state->lane_count;
+ rate = crtc_state->port_clock;
/*
* 1. If port type is eDP or DP,
* else clear to 0b.
*/
val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
- if (type != INTEL_OUTPUT_HDMI)
- val |= COMMON_KEEPER_EN;
- else
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
val &= ~COMMON_KEEPER_EN;
+ else
+ val |= COMMON_KEEPER_EN;
intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
/* 2. Program loadgen select */
intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
/* 5. Program swing and de-emphasis */
- cnl_ddi_vswing_program(encoder, level, type);
+ cnl_ddi_vswing_program(encoder, crtc_state, level);
/* 6. Set training enable to trigger update */
val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
}
static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
- u32 level, int type, int rate)
+ const struct intel_crtc_state *crtc_state,
+ int level)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ const struct cnl_ddi_buf_trans *ddi_translations;
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- const struct cnl_ddi_buf_trans *ddi_translations = NULL;
- u32 n_entries, val;
- int ln;
+ int n_entries, ln;
+ u32 val;
if (INTEL_GEN(dev_priv) >= 12)
- ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
- &n_entries);
+ ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
else if (IS_ELKHARTLAKE(dev_priv))
- ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
- &n_entries);
+ ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
else
- ddi_translations = icl_get_combo_buf_trans(encoder, type, rate,
- &n_entries);
+ ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
if (!ddi_translations)
return;
level = n_entries - 1;
}
- if (type == INTEL_OUTPUT_EDP) {
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
}
static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
- u32 level,
- enum intel_output_type type)
+ const struct intel_crtc_state *crtc_state,
+ int level)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- int width = 0;
- int rate = 0;
+ int width, rate, ln;
u32 val;
- int ln = 0;
-
- if (type == INTEL_OUTPUT_HDMI) {
- width = 4;
- /* Rate is always < than 6GHz for HDMI */
- } else {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- width = intel_dp->lane_count;
- rate = intel_dp->link_rate;
- }
+ width = crtc_state->lane_count;
+ rate = crtc_state->port_clock;
/*
* 1. If port type is eDP or DP,
* else clear to 0b.
*/
val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
- if (type == INTEL_OUTPUT_HDMI)
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
val &= ~COMMON_KEEPER_EN;
else
val |= COMMON_KEEPER_EN;
intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
/* 5. Program swing and de-emphasis */
- icl_ddi_combo_vswing_program(encoder, level, type, rate);
+ icl_ddi_combo_vswing_program(encoder, crtc_state, level);
/* 6. Set training enable to trigger update */
val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
}
static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
- int link_clock, u32 level,
- enum intel_output_type type)
+ const struct intel_crtc_state *crtc_state,
+ int level)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
- u32 n_entries, val;
- int ln, rate = 0;
-
- if (type != INTEL_OUTPUT_HDMI) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- rate = intel_dp->link_rate;
- }
+ int n_entries, ln;
+ u32 val;
- ddi_translations = icl_get_mg_buf_trans(encoder, type, rate,
- &n_entries);
+ ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
/* The table does not have values for level 3 and level 9. */
if (level >= n_entries || level == 3 || level == 9) {
drm_dbg_kms(&dev_priv->drm,
*/
for (ln = 0; ln < 2; ln++) {
val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
- if (link_clock < 300000)
+ if (crtc_state->port_clock < 300000)
val |= CFG_LOW_RATE_LKREN_EN;
else
val &= ~CFG_LOW_RATE_LKREN_EN;
for (ln = 0; ln < 2; ln++) {
val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
- if (link_clock <= 500000) {
+ if (crtc_state->port_clock <= 500000) {
val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
} else {
val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
- if (link_clock <= 500000) {
+ if (crtc_state->port_clock <= 500000) {
val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
} else {
val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
}
static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
- int link_clock,
- u32 level,
- enum intel_output_type type)
+ const struct intel_crtc_state *crtc_state,
+ int level)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
if (intel_phy_is_combo(dev_priv, phy))
- icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
+ icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
else
- icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level,
- type);
+ icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level);
}
static void
-tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
- u32 level, enum intel_output_type type)
+tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int level)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
- u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
- int rate = 0;
-
- if (type != INTEL_OUTPUT_HDMI) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- rate = intel_dp->link_rate;
- }
+ u32 val, dpcnt_mask, dpcnt_val;
+ int n_entries, ln;
- ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate,
- &n_entries);
+ ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
if (level >= n_entries)
level = n_entries - 1;
}
static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
- int link_clock,
- u32 level,
- enum intel_output_type type)
+ const struct intel_crtc_state *crtc_state,
+ int level)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
if (intel_phy_is_combo(dev_priv, phy))
- icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
+ icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
else
- tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type);
+ tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level);
}
-static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels)
+static int translate_signal_level(struct intel_dp *intel_dp,
+ u8 signal_levels)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i;
return 0;
}
-static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
+static int intel_ddi_dp_level(struct intel_dp *intel_dp)
{
u8 train_set = intel_dp->train_set[0];
- int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
- DP_TRAIN_PRE_EMPHASIS_MASK);
+ u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
+ DP_TRAIN_PRE_EMPHASIS_MASK);
return translate_signal_level(intel_dp, signal_levels);
}
static void
-tgl_set_signal_levels(struct intel_dp *intel_dp)
+tgl_set_signal_levels(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
int level = intel_ddi_dp_level(intel_dp);
- tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
- level, encoder->type);
+ tgl_ddi_vswing_sequence(encoder, crtc_state, level);
}
static void
-icl_set_signal_levels(struct intel_dp *intel_dp)
+icl_set_signal_levels(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
int level = intel_ddi_dp_level(intel_dp);
- icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
- level, encoder->type);
+ icl_ddi_vswing_sequence(encoder, crtc_state, level);
}
static void
-cnl_set_signal_levels(struct intel_dp *intel_dp)
+cnl_set_signal_levels(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
int level = intel_ddi_dp_level(intel_dp);
- cnl_ddi_vswing_sequence(encoder, level, encoder->type);
+ cnl_ddi_vswing_sequence(encoder, crtc_state, level);
}
static void
-bxt_set_signal_levels(struct intel_dp *intel_dp)
+bxt_set_signal_levels(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
int level = intel_ddi_dp_level(intel_dp);
- bxt_ddi_vswing_sequence(encoder, level, encoder->type);
+ bxt_ddi_vswing_sequence(encoder, crtc_state, level);
}
static void
-hsw_set_signal_levels(struct intel_dp *intel_dp)
+hsw_set_signal_levels(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
intel_dp->DP |= signal_levels;
if (IS_GEN9_BC(dev_priv))
- skl_ddi_set_iboost(encoder, level, encoder->type);
+ skl_ddi_set_iboost(encoder, crtc_state, level);
intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
int level = intel_ddi_dp_level(intel_dp);
enum transcoder transcoder = crtc_state->cpu_transcoder;
- intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
- crtc_state->lane_count, is_mst);
+ intel_dp_set_link_params(intel_dp,
+ crtc_state->port_clock,
+ crtc_state->lane_count);
intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
*/
/* 7.e Configure voltage swing and related IO settings */
- tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
- encoder->type);
+ tgl_ddi_vswing_sequence(encoder, crtc_state, level);
/*
* 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
* We only configure what the register value will be here. Actual
* enabling happens during link training farther down.
*/
- intel_ddi_init_dp_buf_reg(encoder);
+ intel_ddi_init_dp_buf_reg(encoder, crtc_state);
if (!is_mst)
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
* Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
* (timeout after 800 us)
*/
- intel_dp_start_link_train(intel_dp);
+ intel_dp_start_link_train(intel_dp, crtc_state);
/* 7.k Set DP_TP_CTL link training to Normal */
if (!is_trans_port_sync_mode(crtc_state))
- intel_dp_stop_link_train(intel_dp);
+ intel_dp_stop_link_train(intel_dp, crtc_state);
/* 7.l Configure and enable FEC if needed */
intel_ddi_enable_fec(encoder, crtc_state);
else
drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
- intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
- crtc_state->lane_count, is_mst);
+ intel_dp_set_link_params(intel_dp,
+ crtc_state->port_clock,
+ crtc_state->lane_count);
intel_edp_panel_on(intel_dp);
icl_program_mg_dp_mode(dig_port, crtc_state);
if (INTEL_GEN(dev_priv) >= 11)
- icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
- level, encoder->type);
+ icl_ddi_vswing_sequence(encoder, crtc_state, level);
else if (IS_CANNONLAKE(dev_priv))
- cnl_ddi_vswing_sequence(encoder, level, encoder->type);
+ cnl_ddi_vswing_sequence(encoder, crtc_state, level);
else if (IS_GEN9_LP(dev_priv))
- bxt_ddi_vswing_sequence(encoder, level, encoder->type);
+ bxt_ddi_vswing_sequence(encoder, crtc_state, level);
else
intel_prepare_dp_ddi_buffers(encoder, crtc_state);
lane_reversal);
}
- intel_ddi_init_dp_buf_reg(encoder);
+ intel_ddi_init_dp_buf_reg(encoder, crtc_state);
if (!is_mst)
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_configure_protocol_converter(intel_dp);
intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
true);
intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
- intel_dp_start_link_train(intel_dp);
+ intel_dp_start_link_train(intel_dp, crtc_state);
if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
!is_trans_port_sync_mode(crtc_state))
- intel_dp_stop_link_train(intel_dp);
+ intel_dp_stop_link_train(intel_dp, crtc_state);
intel_ddi_enable_fec(encoder, crtc_state);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- int level = intel_ddi_hdmi_level(encoder);
+ int level = intel_ddi_hdmi_level(encoder, crtc_state);
intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
intel_ddi_clk_select(encoder, crtc_state);
icl_program_mg_dp_mode(dig_port, crtc_state);
if (INTEL_GEN(dev_priv) >= 12)
- tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
- level, INTEL_OUTPUT_HDMI);
+ tgl_ddi_vswing_sequence(encoder, crtc_state, level);
else if (INTEL_GEN(dev_priv) == 11)
- icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
- level, INTEL_OUTPUT_HDMI);
+ icl_ddi_vswing_sequence(encoder, crtc_state, level);
else if (IS_CANNONLAKE(dev_priv))
- cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
+ cnl_ddi_vswing_sequence(encoder, crtc_state, level);
else if (IS_GEN9_LP(dev_priv))
- bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
+ bxt_ddi_vswing_sequence(encoder, crtc_state, level);
else
intel_prepare_hdmi_ddi_buffers(encoder, level);
if (IS_GEN9_BC(dev_priv))
- skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
+ skl_ddi_set_iboost(encoder, crtc_state, level);
intel_ddi_enable_pipe_clock(encoder, crtc_state);
crtc_state->cpu_transcoder)
continue;
- intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder));
+ intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
+ slave_crtc_state);
}
usleep_range(200, 400);
- intel_dp_stop_link_train(enc_to_intel_dp(encoder));
+ intel_dp_stop_link_train(enc_to_intel_dp(encoder),
+ crtc_state);
}
static void intel_enable_ddi_dp(struct intel_atomic_state *state,
enum port port = encoder->port;
if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
- intel_dp_stop_link_train(intel_dp);
+ intel_dp_stop_link_train(intel_dp, crtc_state);
intel_edp_backlight_on(crtc_state, conn_state);
intel_psr_enable(intel_dp, crtc_state, conn_state);
crtc_state->lane_lat_optim_mask);
}
-static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
+static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
}
dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
- if (intel_dp->link_mst)
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
dp_tp_ctl |= DP_TP_CTL_MODE_MST;
- else {
+ } else {
dp_tp_ctl |= DP_TP_CTL_MODE_SST;
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
}
static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
u8 dp_train_pat)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
}
-static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp)
+static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
}
void intel_dp_set_link_params(struct intel_dp *intel_dp,
- int link_rate, u8 lane_count,
- bool link_mst)
+ int link_rate, int lane_count)
{
intel_dp->link_trained = false;
intel_dp->link_rate = link_rate;
intel_dp->lane_count = lane_count;
- intel_dp->link_mst = link_mst;
}
static void intel_dp_prepare(struct intel_encoder *encoder,
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
- intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
- pipe_config->lane_count,
- intel_crtc_has_type(pipe_config,
- INTEL_OUTPUT_DP_MST));
+ intel_dp_set_link_params(intel_dp,
+ pipe_config->port_clock,
+ pipe_config->lane_count);
/*
* There are four kinds of DP registers:
static void
cpt_set_link_train(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
u8 dp_train_pat)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
static void
g4x_set_link_train(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
u8 dp_train_pat)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
/* enable with pattern 1 (as per spec) */
- intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
+ intel_dp_program_link_training_pattern(intel_dp, crtc_state,
+ DP_TRAINING_PATTERN_1);
/*
* Magic for VLV/CHV. We _must_ first set up the register
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_configure_protocol_converter(intel_dp);
- intel_dp_start_link_train(intel_dp);
- intel_dp_stop_link_train(intel_dp);
+ intel_dp_start_link_train(intel_dp, pipe_config);
+ intel_dp_stop_link_train(intel_dp, pipe_config);
if (pipe_config->has_audio) {
drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
}
-static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp)
+static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
}
-static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp)
+static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
}
return DP_TRAIN_PRE_EMPH_LEVEL_3;
}
-static void vlv_set_signal_levels(struct intel_dp *intel_dp)
+static void vlv_set_signal_levels(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
unsigned long demph_reg_value, preemph_reg_value,
return;
}
- vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
+ vlv_set_phy_signal_level(encoder, crtc_state,
+ demph_reg_value, preemph_reg_value,
uniqtranscale_reg_value, 0);
}
-static void chv_set_signal_levels(struct intel_dp *intel_dp)
+static void chv_set_signal_levels(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
u32 deemph_reg_value, margin_reg_value;
return;
}
- chv_set_phy_signal_level(encoder, deemph_reg_value,
- margin_reg_value, uniq_trans_scale);
+ chv_set_phy_signal_level(encoder, crtc_state,
+ deemph_reg_value, margin_reg_value,
+ uniq_trans_scale);
}
static u32 g4x_signal_levels(u8 train_set)
}
static void
-g4x_set_signal_levels(struct intel_dp *intel_dp)
+g4x_set_signal_levels(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 train_set = intel_dp->train_set[0];
}
static void
-snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
+snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 train_set = intel_dp->train_set[0];
}
static void
-ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
+ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 train_set = intel_dp->train_set[0];
intel_de_posting_read(dev_priv, intel_dp->output_reg);
}
-void intel_dp_set_signal_levels(struct intel_dp *intel_dp)
+void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 train_set = intel_dp->train_set[0];
train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
" (max)" : "");
- intel_dp->set_signal_levels(intel_dp);
+ intel_dp->set_signal_levels(intel_dp, crtc_state);
}
void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
u8 dp_train_pat)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
"Using DP training pattern TPS%d\n",
dp_train_pat & train_pat_mask);
- intel_dp->set_link_train(intel_dp, dp_train_pat);
+ intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
}
-void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
+void intel_dp_set_idle_link_train(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
if (intel_dp->set_idle_link_train)
- intel_dp->set_idle_link_train(intel_dp);
+ intel_dp->set_idle_link_train(intel_dp, crtc_state);
}
static void
return test_result;
}
-static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
+static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv =
to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_dp_phy_test_params *data =
&intel_dp->compliance.test_data.phytest;
- struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
u32 pattern_val;
}
static void
-intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
+intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
}
static void
-intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
+intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
trans_ddi_func_ctl_value);
}
-static void intel_dp_process_phy_request(struct intel_dp *intel_dp)
+static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_dp_phy_test_params *data =
&intel_dp->compliance.test_data.phytest;
}
/* retrieve vswing & pre-emphasis setting */
- intel_dp_get_adjust_train(intel_dp, link_status);
+ intel_dp_get_adjust_train(intel_dp, crtc_state, link_status);
- intel_dp_autotest_phy_ddi_disable(intel_dp);
+ intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
- intel_dp_set_signal_levels(intel_dp);
+ intel_dp_set_signal_levels(intel_dp, crtc_state);
- intel_dp_phy_pattern_update(intel_dp);
+ intel_dp_phy_pattern_update(intel_dp, crtc_state);
- intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
+ intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
link_status[DP_DPCD_REV]);
/*
* Validate the cached values of intel_dp->link_rate and
* intel_dp->lane_count before attempting to retrain.
+ *
+ * FIXME would be nice to user the crtc state here, but since
+ * we need to call this from the short HPD handler that seems
+ * a bit hard.
*/
if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
intel_dp->lane_count))
intel_crtc_pch_transcoder(crtc), false);
}
- intel_dp_start_link_train(intel_dp);
- intel_dp_stop_link_train(intel_dp);
+ for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
+ const struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
+
+ /* retrain on the MST master transcoder */
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
+ !intel_dp_mst_is_master_trans(crtc_state))
+ continue;
+
+ intel_dp_start_link_train(intel_dp, crtc_state);
+ intel_dp_stop_link_train(intel_dp, crtc_state);
+ break;
+ }
for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
const struct intel_crtc_state *crtc_state =
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct intel_crtc *crtc;
u32 crtc_mask;
int ret;
drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
encoder->base.base.id, encoder->base.name);
- intel_dp_process_phy_request(intel_dp);
+
+ for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
+ const struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
+
+ /* test on the MST master transcoder */
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
+ !intel_dp_mst_is_master_trans(crtc_state))
+ continue;
+
+ intel_dp_process_phy_request(intel_dp, crtc_state);
+ break;
+ }
return 0;
}
}
}
-void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
- const u8 link_status[DP_LINK_STATUS_SIZE])
+void
+intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const u8 link_status[DP_LINK_STATUS_SIZE])
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 v = 0;
u8 voltage_max;
u8 preemph_max;
- for (lane = 0; lane < intel_dp->lane_count; lane++) {
+ for (lane = 0; lane < crtc_state->lane_count; lane++) {
v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
}
v = min(v, dp_voltage_max(p));
- voltage_max = intel_dp->voltage_max(intel_dp);
+ voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);
drm_WARN_ON_ONCE(&i915->drm,
voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
static bool
intel_dp_set_link_train(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
u8 dp_train_pat)
{
u8 buf[sizeof(intel_dp->train_set) + 1];
int ret, len;
- intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
+ intel_dp_program_link_training_pattern(intel_dp, crtc_state,
+ dp_train_pat);
buf[0] = dp_train_pat;
if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
len = 1;
} else {
/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
- memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
- len = intel_dp->lane_count + 1;
+ memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
+ len = crtc_state->lane_count + 1;
}
ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp,
- u8 dp_train_pat)
+ const struct intel_crtc_state *crtc_state,
+ u8 dp_train_pat)
{
memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
- intel_dp_set_signal_levels(intel_dp);
- return intel_dp_set_link_train(intel_dp, dp_train_pat);
+ intel_dp_set_signal_levels(intel_dp, crtc_state);
+ return intel_dp_set_link_train(intel_dp, crtc_state, dp_train_pat);
}
static bool
-intel_dp_update_link_train(struct intel_dp *intel_dp)
+intel_dp_update_link_train(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
int ret;
- intel_dp_set_signal_levels(intel_dp);
+ intel_dp_set_signal_levels(intel_dp, crtc_state);
ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
- intel_dp->train_set, intel_dp->lane_count);
+ intel_dp->train_set, crtc_state->lane_count);
- return ret == intel_dp->lane_count;
+ return ret == crtc_state->lane_count;
}
-static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
+static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
int lane;
- for (lane = 0; lane < intel_dp->lane_count; lane++)
+ for (lane = 0; lane < crtc_state->lane_count; lane++)
if ((intel_dp->train_set[lane] &
DP_TRAIN_MAX_SWING_REACHED) == 0)
return false;
/* Enable corresponding port and start training pattern 1 */
static bool
-intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
+intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 voltage;
u8 link_bw, rate_select;
if (intel_dp->prepare_link_retrain)
- intel_dp->prepare_link_retrain(intel_dp);
+ intel_dp->prepare_link_retrain(intel_dp, crtc_state);
- intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
+ intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
&link_bw, &rate_select);
if (link_bw)
/* Write the link configuration data */
link_config[0] = link_bw;
- link_config[1] = intel_dp->lane_count;
+ link_config[1] = crtc_state->lane_count;
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
intel_dp->DP |= DP_PORT_EN;
/* clock recovery */
- if (!intel_dp_reset_link_train(intel_dp,
+ if (!intel_dp_reset_link_train(intel_dp, crtc_state,
DP_TRAINING_PATTERN_1 |
DP_LINK_SCRAMBLING_DISABLE)) {
drm_err(&i915->drm, "failed to enable link training\n");
return false;
}
- if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
+ if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
drm_dbg_kms(&i915->drm, "clock recovery OK\n");
return true;
}
voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
/* Update training set as requested by target */
- intel_dp_get_adjust_train(intel_dp, link_status);
- if (!intel_dp_update_link_train(intel_dp)) {
+ intel_dp_get_adjust_train(intel_dp, crtc_state, link_status);
+ if (!intel_dp_update_link_train(intel_dp, crtc_state)) {
drm_err(&i915->drm,
"failed to update link training\n");
return false;
else
voltage_tries = 1;
- if (intel_dp_link_max_vswing_reached(intel_dp))
+ if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
max_vswing_reached = true;
}
* or for 1.4 devices that support it, training Pattern 3 for HBR2
* or 1.2 devices that support it, Training Pattern 2 otherwise.
*/
-static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
+static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
bool source_tps3, sink_tps3, source_tps4, sink_tps4;
sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
if (source_tps4 && sink_tps4) {
return DP_TRAINING_PATTERN_4;
- } else if (intel_dp->link_rate == 810000) {
+ } else if (crtc_state->port_clock == 810000) {
if (!source_tps4)
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
"8.1 Gbps link rate without source HBR3/TPS4 support\n");
sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
if (source_tps3 && sink_tps3) {
return DP_TRAINING_PATTERN_3;
- } else if (intel_dp->link_rate >= 540000) {
+ } else if (crtc_state->port_clock >= 540000) {
if (!source_tps3)
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
}
static bool
-intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
+intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int tries;
u8 link_status[DP_LINK_STATUS_SIZE];
bool channel_eq = false;
- training_pattern = intel_dp_training_pattern(intel_dp);
+ training_pattern = intel_dp_training_pattern(intel_dp, crtc_state);
/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
if (training_pattern != DP_TRAINING_PATTERN_4)
training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
/* channel equalization */
- if (!intel_dp_set_link_train(intel_dp,
+ if (!intel_dp_set_link_train(intel_dp, crtc_state,
training_pattern)) {
drm_err(&i915->drm, "failed to start channel equalization\n");
return false;
/* Make sure clock is still ok */
if (!drm_dp_clock_recovery_ok(link_status,
- intel_dp->lane_count)) {
+ crtc_state->lane_count)) {
intel_dp_dump_link_status(link_status);
drm_dbg_kms(&i915->drm,
"Clock recovery check failed, cannot "
}
if (drm_dp_channel_eq_ok(link_status,
- intel_dp->lane_count)) {
+ crtc_state->lane_count)) {
channel_eq = true;
drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training "
"successful\n");
}
/* Update training set as requested by target */
- intel_dp_get_adjust_train(intel_dp, link_status);
- if (!intel_dp_update_link_train(intel_dp)) {
+ intel_dp_get_adjust_train(intel_dp, crtc_state, link_status);
+ if (!intel_dp_update_link_train(intel_dp, crtc_state)) {
drm_err(&i915->drm,
"failed to update link training\n");
break;
"Channel equalization failed 5 times\n");
}
- intel_dp_set_idle_link_train(intel_dp);
+ intel_dp_set_idle_link_train(intel_dp, crtc_state);
return channel_eq;
}
-void intel_dp_stop_link_train(struct intel_dp *intel_dp)
+void intel_dp_stop_link_train(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
intel_dp->link_trained = true;
- intel_dp_set_link_train(intel_dp,
+ intel_dp_set_link_train(intel_dp, crtc_state,
DP_TRAINING_PATTERN_DISABLE);
}
void
-intel_dp_start_link_train(struct intel_dp *intel_dp)
+intel_dp_start_link_train(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_connector *intel_connector = intel_dp->attached_connector;
- if (!intel_dp_link_training_clock_recovery(intel_dp))
+ if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state))
goto failure_handling;
- if (!intel_dp_link_training_channel_equalization(intel_dp))
+ if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state))
goto failure_handling;
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
"[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d",
intel_connector->base.base.id,
intel_connector->base.name,
- intel_dp->link_rate, intel_dp->lane_count);
+ crtc_state->port_clock, crtc_state->lane_count);
return;
failure_handling:
"[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
intel_connector->base.base.id,
intel_connector->base.name,
- intel_dp->link_rate, intel_dp->lane_count);
+ crtc_state->port_clock, crtc_state->lane_count);
if (intel_dp->hobl_active) {
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
"Link Training failed with HOBL active, not enabling it from now on");
intel_dp->hobl_failed = true;
} else if (intel_dp_get_link_train_fallback_values(intel_dp,
- intel_dp->link_rate,
- intel_dp->lane_count)) {
+ crtc_state->port_clock,
+ crtc_state->lane_count)) {
return;
}
projects / kernel.git / commitdiff